any_div.tan.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 47 行

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tco
Slack          : -8.716 ns
Required Time  : 0.100 ns
Actual Time    : 8.816 ns
From           : clkdiv1
To             : clkdiv
From Clock     : clk
To Clock       : --
Failed Paths   : 1

Type           : Clock Setup: 'clk'
Slack          : 5.492 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 221.83 MHz ( period = 4.508 ns )
From           : cnt1[0]
To             : cnt1[31]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : -1.150 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : clkdiv1~_Duplicate_1
To             : clkdiv1~_Duplicate_1
From Clock     : clk
To Clock       : clk
Failed Paths   : 2

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 3

--------------------------------------------------------------------------------------