sub4.fit.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Wed Mar 07 16:07:17 2007
Quartus II Version : 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
Revision Name : sub4
Top-level Entity Name : sub4
Family : Cyclone II
Device : EP2C8T144C8
Timing Models : Final
Total logic elements : 6 / 8,256 ( < 1 % )
Total registers : 0
Total pins : 14 / 85 ( 16 % )
Total virtual pins : 0
Total memory bits : 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )