sub4.vhd

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sub4 is
port(a:in std_logic_vector(3 downto 0);
     b:in std_logic_vector(3 downto 0);
     ci:in std_logic;
     dout:out std_logic_vector(3 downto 0);
     cout:out std_logic);
end;
architecture one of sub4 is
signal temp:std_logic_vector(4 downto 0);
begin
temp<=('0'&a)-b-ci;
dout<=temp(3 downto 0);
cout<=temp(4);
end;