bianma8_3.hier_info

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· HIER_INFO 代码 · 共 31 行

|bianma8_3
i[0] => Mux0.IN263
i[0] => Mux1.IN263
i[0] => Mux2.IN263
i[1] => Mux0.IN262
i[1] => Mux1.IN262
i[1] => Mux2.IN262
i[2] => Mux0.IN261
i[2] => Mux1.IN261
i[2] => Mux2.IN261
i[3] => Mux0.IN260
i[3] => Mux1.IN260
i[3] => Mux2.IN260
i[4] => Mux0.IN259
i[4] => Mux1.IN259
i[4] => Mux2.IN259
i[5] => Mux0.IN258
i[5] => Mux1.IN258
i[5] => Mux2.IN258
i[6] => Mux0.IN257
i[6] => Mux1.IN257
i[6] => Mux2.IN257
i[7] => Mux0.IN256
i[7] => Mux1.IN256
i[7] => Mux2.IN256
y[0] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
y[1] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
y[2] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE