div5.vhd

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· VHDL 代码 · 共 58 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div5 is
generic(n:integer:=5);
port(clk:in std_logic;-------时钟
     div5:out std_logic);----输出5分频信号
end;
architecture one of div5 is
	signal cnt1:integer:=0;---计数器1
	signal cnt2:integer:=0;---计数器2
	signal clk_temp1:std_logic;
	signal clk_temp2:std_logic;
begin
--------------------上升沿触发计数器进程
process(clk)
begin
if clk'event and clk='1' then
	if cnt1=n-1 then
	cnt1<=0;
	else cnt1<=cnt1+1;
	end if;
end if;
end process;
---------------------下降沿触发计数器进程
process(clk)
begin
if clk'event and clk='0' then
	if cnt2=n-1 then
	cnt2<=0;
	else cnt2<=cnt2+1;
	end if;
end if;
end process;
-----------------------上升沿触发计数器的计数控制进程
process(clk)
begin
if clk'event and clk='1' then
	if cnt1=0 then
	  clk_temp1<='1';
	elsif cnt1=(n-1)/2 then
	  clk_temp1<='0';
	end if;
end if;
end process;
-----------------------下降沿触发计数器的计数控制进程
process(clk)
begin
if clk'event and clk='0' then
	if cnt2=0 then
	  clk_temp2<='1';
	elsif cnt2=(n-1)/2  then
	  clk_temp2<='0';
	end if;
end if;
end process;
	div5<=clk_temp1 or clk_temp2;---将两个计数器控制的信号采用或逻辑
end;