div5_1.vhd

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· VHDL 代码 · 共 60 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div5_1 is
port(clk:in std_logic;-------时钟
     div5:buffer std_logic);----输出5分频信号
end;
architecture one of div5_1 is
	signal cnt1:std_logic_vector(2 downto 0);---计数器1
	signal cnt2:std_logic_vector(2 downto 0);---计数器2
    signal out_temp:std_logic;
	constant m1:integer:=4;----计数器控制端1，m1=N－1
	constant m2:integer:=3;----计数器控制端2，m2=(N+1)/2
begin
--------------------上升沿触发计数器进程
process(clk)
begin
if clk'event and clk='1' then
	if cnt1=m1 then
	cnt1<="000";
	else cnt1<=cnt1+1;
	end if;
end if;
end process;
---------------------下降沿触发计数器进程
process(clk)
begin
if clk'event and clk='0' then
	if cnt2=m1 then
	cnt2<="000";
	else cnt2<=cnt2+1;
	end if;
end if;
end process;
---------------------------
process(cnt1,cnt2)
begin
    if cnt1=1 then
		if cnt2=0 then
		out_temp<='1';
		else out_temp<='0';
		end if;
	elsif cnt1=m2 then
		if cnt2=m2 then
		out_temp<='1';
		else out_temp<='0';
		end if;
	else 
	out_temp<='0';
	end if;
end process;
------------------------------------------
process(out_temp,clk)
begin
if out_temp'event and out_temp='1' then
	div5<=not div5;
end if;
end process;
end;