cymometer.fit.smsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Mon Apr 09 20:33:03 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off cymometer -c cymometer
Info: Selected device EP2C8T144C8 for design "cymometer"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 276 of 276 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 2 pins of 17 total pins
    Info: Pin scan[6] not assigned to an exact location on the device
    Info: Pin scan[7] not assigned to an exact location on the device
Info: Automatically promoted node clkin (placed in PIN 18 (CLK1, LVDSCLK0n, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Automatically promoted node sysclk (placed in PIN 17 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G0
Info: Automatically promoted node Mux19~55 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 0 input, 2 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  13 pins available
        Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 4 total pin(s) used --  19 pins available
        Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 6 total pin(s) used --  15 pins available
        Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 4 total pin(s) used --  20 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 7.121 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X24_Y10; Fanout = 7; REG Node = 'cntp1[0]'
    Info: 2: + IC(1.389 ns) + CELL(0.206 ns) = 1.595 ns; Loc. = LAB_X24_Y11; Fanout = 10; COMB Node = 'Equal1~53'
    Info: 3: + IC(1.167 ns) + CELL(0.370 ns) = 3.132 ns; Loc. = LAB_X24_Y9; Fanout = 2; COMB Node = 'cntp3[0]~1089'
    Info: 4: + IC(1.331 ns) + CELL(0.206 ns) = 4.669 ns; Loc. = LAB_X25_Y11; Fanout = 5; COMB Node = 'cntp4[0]~1094'
    Info: 5: + IC(0.605 ns) + CELL(0.202 ns) = 5.476 ns; Loc. = LAB_X25_Y11; Fanout = 3; COMB Node = 'cntp4[3]~1095'
    Info: 6: + IC(0.913 ns) + CELL(0.624 ns) = 7.013 ns; Loc. = LAB_X25_Y13; Fanout = 1; COMB Node = 'cntp4[3]~1099'
    Info: 7: + IC(0.000 ns) + CELL(0.108 ns) = 7.121 ns; Loc. = LAB_X25_Y13; Fanout = 4; REG Node = 'cntp4[3]'
    Info: Total cell delay = 1.716 ns ( 24.10 % )
    Info: Total interconnect delay = 5.405 ns ( 75.90 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location X23_Y10 to location X34_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 15 output pins without output pin load capacitance assignment
    Info: Pin "seg7[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 174 megabytes of memory during processing
    Info: Processing ended: Mon Apr 09 20:33:12 2007
    Info: Elapsed time: 00:00:09