mult.fit.smsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Apr 25 15:12:37 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off mult -c mult
Info: Automatically selected device EP1S10F484C5 for design mult
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 35 of 35 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1S20F484C5 is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
    Info: Pin ~DATA0~ is reserved at location L8
Warning: No exact pin location assignment(s) for 33 pins of 33 total pins
    Info: Pin result[0] not assigned to an exact location on the device
    Info: Pin result[1] not assigned to an exact location on the device
    Info: Pin result[2] not assigned to an exact location on the device
    Info: Pin result[3] not assigned to an exact location on the device
    Info: Pin result[4] not assigned to an exact location on the device
    Info: Pin result[5] not assigned to an exact location on the device
    Info: Pin result[6] not assigned to an exact location on the device
    Info: Pin result[7] not assigned to an exact location on the device
    Info: Pin result[8] not assigned to an exact location on the device
    Info: Pin result[9] not assigned to an exact location on the device
    Info: Pin result[10] not assigned to an exact location on the device
    Info: Pin result[11] not assigned to an exact location on the device
    Info: Pin result[12] not assigned to an exact location on the device
    Info: Pin result[13] not assigned to an exact location on the device
    Info: Pin result[14] not assigned to an exact location on the device
    Info: Pin result[15] not assigned to an exact location on the device
    Info: Pin dataa[0] not assigned to an exact location on the device
    Info: Pin dataa[1] not assigned to an exact location on the device
    Info: Pin dataa[2] not assigned to an exact location on the device
    Info: Pin dataa[3] not assigned to an exact location on the device
    Info: Pin dataa[4] not assigned to an exact location on the device
    Info: Pin dataa[5] not assigned to an exact location on the device
    Info: Pin dataa[6] not assigned to an exact location on the device
    Info: Pin dataa[7] not assigned to an exact location on the device
    Info: Pin datab[0] not assigned to an exact location on the device
    Info: Pin datab[1] not assigned to an exact location on the device
    Info: Pin datab[2] not assigned to an exact location on the device
    Info: Pin datab[3] not assigned to an exact location on the device
    Info: Pin datab[4] not assigned to an exact location on the device
    Info: Pin datab[5] not assigned to an exact location on the device
    Info: Pin datab[6] not assigned to an exact location on the device
    Info: Pin datab[7] not assigned to an exact location on the device
    Info: Pin clock not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 33 (unused VREF, 3.30 VCCIO, 17 input, 16 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y0 to location X9_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 205 megabytes of memory during processing
    Info: Processing ended: Wed Apr 25 15:12:54 2007
    Info: Elapsed time: 00:00:17