decoder.fit.smsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Apr 19 15:40:19 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off decoder -c decoder
Info: Selected device EP2C8T144C8 for design "decoder"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 340 of 340 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 43 pins of 43 total pins
    Info: Pin scan[0] not assigned to an exact location on the device
    Info: Pin scan[1] not assigned to an exact location on the device
    Info: Pin scan[2] not assigned to an exact location on the device
    Info: Pin scan[3] not assigned to an exact location on the device
    Info: Pin scan[4] not assigned to an exact location on the device
    Info: Pin scan[5] not assigned to an exact location on the device
    Info: Pin scan[6] not assigned to an exact location on the device
    Info: Pin scan[7] not assigned to an exact location on the device
    Info: Pin seg7[0] not assigned to an exact location on the device
    Info: Pin seg7[1] not assigned to an exact location on the device
    Info: Pin seg7[2] not assigned to an exact location on the device
    Info: Pin seg7[3] not assigned to an exact location on the device
    Info: Pin seg7[4] not assigned to an exact location on the device
    Info: Pin seg7[5] not assigned to an exact location on the device
    Info: Pin seg7[6] not assigned to an exact location on the device
    Info: Pin dp not assigned to an exact location on the device
    Info: Pin clk20mhz not assigned to an exact location on the device
    Info: Pin distance_in[4] not assigned to an exact location on the device
    Info: Pin distance_in[10] not assigned to an exact location on the device
    Info: Pin distance_in[1] not assigned to an exact location on the device
    Info: Pin distance_in[9] not assigned to an exact location on the device
    Info: Pin distance_in[3] not assigned to an exact location on the device
    Info: Pin distance_in[8] not assigned to an exact location on the device
    Info: Pin distance_in[0] not assigned to an exact location on the device
    Info: Pin distance_in[5] not assigned to an exact location on the device
    Info: Pin distance_in[6] not assigned to an exact location on the device
    Info: Pin distance_in[7] not assigned to an exact location on the device
    Info: Pin distance_in[2] not assigned to an exact location on the device
    Info: Pin distance_in[11] not assigned to an exact location on the device
    Info: Pin distance_in[12] not assigned to an exact location on the device
    Info: Pin money_in[4] not assigned to an exact location on the device
    Info: Pin money_in[10] not assigned to an exact location on the device
    Info: Pin money_in[1] not assigned to an exact location on the device
    Info: Pin money_in[9] not assigned to an exact location on the device
    Info: Pin money_in[3] not assigned to an exact location on the device
    Info: Pin money_in[8] not assigned to an exact location on the device
    Info: Pin money_in[0] not assigned to an exact location on the device
    Info: Pin money_in[5] not assigned to an exact location on the device
    Info: Pin money_in[6] not assigned to an exact location on the device
    Info: Pin money_in[7] not assigned to an exact location on the device
    Info: Pin money_in[2] not assigned to an exact location on the device
    Info: Pin money_in[11] not assigned to an exact location on the device
    Info: Pin money_in[12] not assigned to an exact location on the device
Info: Automatically promoted node clk20mhz (placed in PIN 17 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Automatically promoted node clk1khz 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node clk1khz~2
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 42 (unused VREF, 3.30 VCCIO, 26 input, 16 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  14 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 6.480 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y12; Fanout = 5; REG Node = 'comb1[0]'
    Info: 2: + IC(1.329 ns) + CELL(0.621 ns) = 1.950 ns; Loc. = LAB_X21_Y12; Fanout = 1; COMB Node = 'LessThan0~192'
    Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 2.036 ns; Loc. = LAB_X21_Y12; Fanout = 1; COMB Node = 'LessThan0~194'
    Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 2.122 ns; Loc. = LAB_X21_Y12; Fanout = 1; COMB Node = 'LessThan0~196'
    Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 2.208 ns; Loc. = LAB_X21_Y12; Fanout = 1; COMB Node = 'LessThan0~198'
    Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 2.294 ns; Loc. = LAB_X21_Y12; Fanout = 1; COMB Node = 'LessThan0~200'
    Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 2.380 ns; Loc. = LAB_X21_Y12; Fanout = 1; COMB Node = 'LessThan0~202'
    Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 2.466 ns; Loc. = LAB_X21_Y12; Fanout = 1; COMB Node = 'LessThan0~204'
    Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.552 ns; Loc. = LAB_X21_Y12; Fanout = 1; COMB Node = 'LessThan0~206'
    Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.638 ns; Loc. = LAB_X21_Y12; Fanout = 1; COMB Node = 'LessThan0~208'
    Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.724 ns; Loc. = LAB_X21_Y12; Fanout = 1; COMB Node = 'LessThan0~210'
    Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.810 ns; Loc. = LAB_X21_Y12; Fanout = 1; COMB Node = 'LessThan0~212'
    Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.896 ns; Loc. = LAB_X21_Y12; Fanout = 1; COMB Node = 'LessThan0~214'
    Info: 14: + IC(0.000 ns) + CELL(0.506 ns) = 3.402 ns; Loc. = LAB_X21_Y12; Fanout = 31; COMB Node = 'LessThan0~215'
    Info: 15: + IC(0.841 ns) + CELL(0.614 ns) = 4.857 ns; Loc. = LAB_X19_Y12; Fanout = 1; COMB Node = 'comb1_a~446'
    Info: 16: + IC(0.864 ns) + CELL(0.651 ns) = 6.372 ns; Loc. = LAB_X23_Y12; Fanout = 1; COMB Node = 'comb1_a~447'
    Info: 17: + IC(0.000 ns) + CELL(0.108 ns) = 6.480 ns; Loc. = LAB_X23_Y12; Fanout = 3; REG Node = 'comb1_a[3]'
    Info: Total cell delay = 3.446 ns ( 53.18 % )
    Info: Total interconnect delay = 3.034 ns ( 46.82 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location X11_Y10 to location X22_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 16 output pins without output pin load capacitance assignment
    Info: Pin "scan[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dp" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 174 megabytes of memory during processing
    Info: Processing ended: Thu Apr 19 15:40:32 2007
    Info: Elapsed time: 00:00:13