ping_pang.fit.smsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Apr 10 16:38:58 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ping_pang -c ping_pang
Info: Selected device EP2C8T144C8 for design "ping_pang"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 8 pins of 33 total pins
    Info: Pin seg7[0] not assigned to an exact location on the device
    Info: Pin seg7[1] not assigned to an exact location on the device
    Info: Pin seg7[2] not assigned to an exact location on the device
    Info: Pin seg7[3] not assigned to an exact location on the device
    Info: Pin seg7[4] not assigned to an exact location on the device
    Info: Pin seg7[5] not assigned to an exact location on the device
    Info: Pin seg7[6] not assigned to an exact location on the device
    Info: Pin clk1khz not assigned to an exact location on the device
Info: Automatically promoted node clk1khz (placed in PIN 17 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Automatically promoted node clk1_2hz 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node clk1_2hz~21
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 7 (unused VREF, 3.30 VCCIO, 0 input, 7 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  14 pins available
        Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 9 total pin(s) used --  14 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available
        Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 16 total pin(s) used --  8 pins available
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "clk" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[0]" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[1]" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[2]" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[3]" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[4]" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[5]" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[6]" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 6.273 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y15; Fanout = 4; REG Node = 'shift_1[15]'
    Info: 2: + IC(1.356 ns) + CELL(0.202 ns) = 1.558 ns; Loc. = LAB_X14_Y15; Fanout = 1; COMB Node = 'Equal1~173'
    Info: 3: + IC(0.187 ns) + CELL(0.623 ns) = 2.368 ns; Loc. = LAB_X14_Y15; Fanout = 8; COMB Node = 'Equal1~174'
    Info: 4: + IC(0.605 ns) + CELL(0.206 ns) = 3.179 ns; Loc. = LAB_X14_Y15; Fanout = 3; COMB Node = 'LessThan0~159'
    Info: 5: + IC(0.441 ns) + CELL(0.370 ns) = 3.990 ns; Loc. = LAB_X14_Y15; Fanout = 1; COMB Node = 'shift_1[1]~5210'
    Info: 6: + IC(0.187 ns) + CELL(0.571 ns) = 4.748 ns; Loc. = LAB_X14_Y15; Fanout = 14; COMB Node = 'shift_1[1]~5213'
    Info: 7: + IC(0.670 ns) + CELL(0.855 ns) = 6.273 ns; Loc. = LAB_X13_Y15; Fanout = 4; REG Node = 'shift_1[10]'
    Info: Total cell delay = 2.827 ns ( 45.07 % )
    Info: Total interconnect delay = 3.446 ns ( 54.93 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%
    Info: The peak interconnect region extends from location X11_Y10 to location X22_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 27 output pins without output pin load capacitance assignment
    Info: Pin "shift[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "shift[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 12 warnings
    Info: Allocated 174 megabytes of memory during processing
    Info: Processing ended: Tue Apr 10 16:39:09 2007
    Info: Elapsed time: 00:00:11