jp4x4_1.fit.smsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sat Apr 07 15:48:29 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off jp4x4_1 -c jp4x4_1
Info: Selected device EP2C8T144C8 for design "jp4x4_1"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 88 of 88 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 25 pins of 25 total pins
    Info: Pin kbrow[0] not assigned to an exact location on the device
    Info: Pin kbrow[1] not assigned to an exact location on the device
    Info: Pin kbrow[2] not assigned to an exact location on the device
    Info: Pin kbrow[3] not assigned to an exact location on the device
    Info: Pin seg7_out[0] not assigned to an exact location on the device
    Info: Pin seg7_out[1] not assigned to an exact location on the device
    Info: Pin seg7_out[2] not assigned to an exact location on the device
    Info: Pin seg7_out[3] not assigned to an exact location on the device
    Info: Pin seg7_out[4] not assigned to an exact location on the device
    Info: Pin seg7_out[5] not assigned to an exact location on the device
    Info: Pin seg7_out[6] not assigned to an exact location on the device
    Info: Pin scan[0] not assigned to an exact location on the device
    Info: Pin scan[1] not assigned to an exact location on the device
    Info: Pin scan[2] not assigned to an exact location on the device
    Info: Pin scan[3] not assigned to an exact location on the device
    Info: Pin scan[4] not assigned to an exact location on the device
    Info: Pin scan[5] not assigned to an exact location on the device
    Info: Pin scan[6] not assigned to an exact location on the device
    Info: Pin scan[7] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin kbcol[0] not assigned to an exact location on the device
    Info: Pin kbcol[1] not assigned to an exact location on the device
    Info: Pin kbcol[2] not assigned to an exact location on the device
    Info: Pin kbcol[3] not assigned to an exact location on the device
    Info: Pin start not assigned to an exact location on the device
Info: Automatically promoted node clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Automatically promoted node fn~3 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node start (placed in PIN 18 (CLK1, LVDSCLK0n, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node dat[0]
        Info: Destination node dat[1]
        Info: Destination node dat[2]
        Info: Destination node dat[3]
        Info: Destination node dat[4]
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 23 (unused VREF, 3.30 VCCIO, 4 input, 19 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  13 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 1.800 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y12; Fanout = 15; REG Node = 'sta[0]'
    Info: 2: + IC(0.511 ns) + CELL(0.370 ns) = 0.881 ns; Loc. = LAB_X15_Y12; Fanout = 1; COMB Node = 'Mux23~13'
    Info: 3: + IC(0.441 ns) + CELL(0.370 ns) = 1.692 ns; Loc. = LAB_X15_Y12; Fanout = 1; COMB Node = 'Mux23~14'
    Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.800 ns; Loc. = LAB_X15_Y12; Fanout = 1; REG Node = 'seg7[2]'
    Info: Total cell delay = 0.848 ns ( 47.11 % )
    Info: Total interconnect delay = 0.952 ns ( 52.89 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X11_Y10 to location X22_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 19 output pins without output pin load capacitance assignment
    Info: Pin "kbrow[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "kbrow[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "kbrow[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "kbrow[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7_out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7_out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7_out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7_out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7_out[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7_out[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7_out[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: Following 8 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin scan[0] has VCC driving its datain port
    Info: Pin scan[1] has GND driving its datain port
    Info: Pin scan[2] has GND driving its datain port
    Info: Pin scan[3] has GND driving its datain port
    Info: Pin scan[4] has GND driving its datain port
    Info: Pin scan[5] has GND driving its datain port
    Info: Pin scan[6] has GND driving its datain port
    Info: Pin scan[7] has GND driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 4 warnings
    Info: Allocated 174 megabytes of memory during processing
    Info: Processing ended: Sat Apr 07 15:48:37 2007
    Info: Elapsed time: 00:00:08