sin.fit.smsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Apr 26 10:48:48 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off sin -c sin
Info: Selected device EP2C8T144C8 for design "sin"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 29 of 29 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: No exact pin location assignment(s) for 9 pins of 9 total pins
    Info: Pin q[7] not assigned to an exact location on the device
    Info: Pin q[6] not assigned to an exact location on the device
    Info: Pin q[5] not assigned to an exact location on the device
    Info: Pin q[4] not assigned to an exact location on the device
    Info: Pin q[3] not assigned to an exact location on the device
    Info: Pin q[2] not assigned to an exact location on the device
    Info: Pin q[1] not assigned to an exact location on the device
    Info: Pin q[0] not assigned to an exact location on the device
    Info: Pin clock not assigned to an exact location on the device
Info: Automatically promoted node clock (placed in PIN 17 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 8 (unused VREF, 3.30 VCCIO, 0 input, 8 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  14 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is memory to memory delay of 3.641 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y2; Fanout = 1; MEM Node = 'sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a7~porta_address_reg5'
    Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X11_Y2; Fanout = 1; MEM Node = 'sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[7]'
    Info: Total cell delay = 3.641 ns ( 100.00 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y0 to location X10_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 8 output pins without output pin load capacitance assignment
    Info: Pin "q[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "q[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "q[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "q[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "q[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "q[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "q[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "q[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 176 megabytes of memory during processing
    Info: Processing ended: Thu Apr 26 10:49:00 2007
    Info: Elapsed time: 00:00:12