jiao_tong.fit.smsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Jun 01 16:22:56 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off jiao_tong -c jiao_tong
Info: Selected device EP2C8T144C8 for design "jiao_tong"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 7 pins of 17 total pins
    Info: Pin seg7[0] not assigned to an exact location on the device
    Info: Pin seg7[1] not assigned to an exact location on the device
    Info: Pin seg7[2] not assigned to an exact location on the device
    Info: Pin seg7[3] not assigned to an exact location on the device
    Info: Pin seg7[4] not assigned to an exact location on the device
    Info: Pin seg7[5] not assigned to an exact location on the device
    Info: Pin seg7[6] not assigned to an exact location on the device
Info: Automatically promoted node clk1hz 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node scan[0]
        Info: Destination node scan[1]
        Info: Destination node Mux0~13
        Info: Destination node Mux11~14
        Info: Destination node Mux12~14
        Info: Destination node Mux13~14
        Info: Destination node seg7~245
        Info: Destination node seg7~246
        Info: Destination node seg7~247
        Info: Destination node seg7~248
        Info: Non-global destination nodes limited to 10 nodes
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 7 (unused VREF, 3.30 VCCIO, 0 input, 7 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  14 pins available
        Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 6 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available
        Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 3 total pin(s) used --  21 pins available
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "data_out[0]" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[1]" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[2]" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[3]" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[4]" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[5]" is assigned to location or region, but does not exist in design
    Warning: Node "data_out[6]" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Estimated most critical path is register to register delay of 4.027 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y11; Fanout = 5; REG Node = 'stx.st1'
    Info: 2: + IC(0.675 ns) + CELL(0.206 ns) = 0.881 ns; Loc. = LAB_X14_Y11; Fanout = 2; COMB Node = 'qh[1]~488'
    Info: 3: + IC(0.467 ns) + CELL(0.650 ns) = 1.998 ns; Loc. = LAB_X13_Y11; Fanout = 1; COMB Node = 'qh[1]~489'
    Info: 4: + IC(0.605 ns) + CELL(0.206 ns) = 2.809 ns; Loc. = LAB_X13_Y11; Fanout = 3; COMB Node = 'qh[1]~490'
    Info: 5: + IC(0.363 ns) + CELL(0.855 ns) = 4.027 ns; Loc. = LAB_X13_Y11; Fanout = 5; REG Node = 'qh[1]'
    Info: Total cell delay = 1.917 ns ( 47.60 % )
    Info: Total interconnect delay = 2.110 ns ( 52.40 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y10 to location X10_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: Started post-fitting delay annotation
Warning: Found 15 output pins without output pin load capacitance assignment
    Info: Pin "scan[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "scan[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "seg7[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ra" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ya" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ga" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "rb" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "yb" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "gb" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 11 warnings
    Info: Allocated 176 megabytes of memory during processing
    Info: Processing ended: Fri Jun 01 16:23:14 2007
    Info: Elapsed time: 00:00:18