dds_top.fit.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Sat May 05 19:29:11 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : dds_top
Top-level Entity Name : dds_top
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 124 / 10,570 ( 1 % )
Total pins : 62 / 336 ( 18 % )
Total virtual pins : 0
Total memory bits : 10,240 / 920,448 ( 1 % )
DSP block 9-bit elements : 2 / 48 ( 4 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )