prev_cmp_m.map.qmsg

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· QMSG 代码 · 共 20 行 · 第 1/4 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 09 15:48:17 2007 " "Info: Processing started: Wed May 09 15:48:17 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off m -c m " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off m -c m" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/70/DSPBuilder/Altlib/DSPBUILDERPACK.VHD 2 0 " "Info: Found 2 design units, including 0 entities, in source file e:/altera/70/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dspbuilderblock " "Info: Found design unit 1: dspbuilderblock" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 dspbuilderblock-body " "Info: Found design unit 2: dspbuilderblock-body" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 1279 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "syn_pipeline e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD(1626) " "Warning (10335): Unrecognized synthesis attribute \"syn_pipeline\" at e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD(1626)" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1626 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0}