m.tan.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 67 行

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.852 ns
From           : sclrp
To             : SDelay:Delayi|result[0]
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.785 ns
From           : SDelay:Delay2i|DelayLine[6][0]
To             : Output
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.519 ns
From           : sclrp
To             : SDelay:Delay1i|DelayLine[1][0]
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : 18.936 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : Restricted to 420.17 MHz ( period = 2.380 ns )
From           : SDelay:Delay1i|DelayLine[1][0]
To             : SDelay:Delayi|result[0]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Clock Hold: 'clock'
Slack          : 0.517 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : SDelay:Delay1i|DelayLine[0][0]
To             : SDelay:Delay1i|DelayLine[1][0]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------