ask.tan.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.919 ns
From           : data_in
To             : dds:ddsi|AltiMult:Producti|databint[2]~_Duplicate_2
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.135 ns
From           : dds:ddsi|AltiMult:Producti|resdtb[14]
To             : data_out[4]
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.291 ns
From           : Fword[1]
To             : dds:ddsi|SDelay:Delayi|result[1]
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : 10.767 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 108.31 MHz ( period = 9.233 ns )
From           : dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9
To             : dds:ddsi|AltiMult:Producti|resdtb[17]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Clock Hold: 'clock'
Slack          : 0.531 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31]
To             : dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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