fsk.fnsim.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sAltrPropagate dds:ddsi\|SDelay:Delayi\|sAltrPropagate:u0 " "Info: Elaborating entity \"sAltrPropagate\" for hierarchy \"dds:ddsi\|SDelay:Delayi\|sAltrPropagate:u0\"" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "u0" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1297 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AltiMult dds:ddsi\|AltiMult:Producti " "Info: Elaborating entity \"AltiMult\" for hierarchy \"dds:ddsi\|AltiMult:Producti\"" {  } { { "dds.vhd" "Producti" { Text "D:/my_eda3/ASK_FSK/dds.vhd" 116 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SAdderSub dds:ddsi\|SAdderSub:ParallelAdderSubtractori " "Info: Elaborating entity \"SAdderSub\" for hierarchy \"dds:ddsi\|SAdderSub:ParallelAdderSubtractori\"" {  } { { "dds.vhd" "ParallelAdderSubtractori" { Text "D:/my_eda3/ASK_FSK/dds.vhd" 137 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/70/quartus/libraries/megafunctions/LPM_ADD_SUB.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/LPM_ADD_SUB.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "LPM_ADD_SUB.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/LPM_ADD_SUB.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ADD_SUB dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0 " "Info: Elaborating entity \"LPM_ADD_SUB\" for hierarchy \"dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0\"" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "\\pip:genaa:U0" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1876 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0 " "Info: Elaborated megafunction instantiation \"dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0\"" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1876 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/70/quartus/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0\|addcore:adder0\[0\] " "Info: Elaborating entity \"addcore\" for hierarchy \"dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0\|addcore:adder0\[0\]\"" {  } { { "LPM_ADD_SUB.tdf" "adder0\[0\]" { Text "e:/altera/70/quartus/libraries/megafunctions/LPM_ADD_SUB.tdf" 221 11 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0\|addcore:adder0\[0\] dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0 " "Info: Elaborated megafunction instantiation \"dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0\|addcore:adder0\[0\]\", which is child of megafunction instantiation \"dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0\"" {  } { { "LPM_ADD_SUB.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/LPM_ADD_SUB.tdf" 221 11 0 } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1876 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0 " "Info: Instantiated megafunction \"dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 33 " "Info: Parameter \"LPM_WIDTH\" = \"33\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 1 " "Info: Parameter \"LPM_PIPELINE\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_ADD_SUB " "Info: Parameter \"LPM_TYPE\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT UNUSED " "Info: Parameter \"LPM_HINT\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1876 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}