ad1674ctrl.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

--ad1674控制器
--ad1674的时钟为20MHz;

library ieee;
use ieee.std_logic_1164.all;
entity ad1674ctrl is 
 port(D:in std_logic_vector(11 downto 0);
      clk:in std_logic; --------状态机时钟
      status:in std_logic; -- --ad1674状态信号
      clkn:out std_logic;  -----内部锁存信号lock的测试端
      cs,a0,rc,k12x8:out std_logic;-------------ad1674控制信号
      q:out std_logic_vector(11 downto 0));----锁存数据输出
end ad1674ctrl;
architecture one of ad1674ctrl is
 type states is (st0,st1,st2,st3,st4);
  signal current_state,next_state:states:=st0; -----状态转换及信号控制进程
  signal regl:std_logic_vector(11 downto 0);
  signal lock:std_logic;
begin
      k12x8<='1';----lock0<=lock;
pro:process(current_state,status) --- --状态转换及信号控制进程
  begin 
   case current_state is
   when st0=>cs<='1';a0<='1';rc<='1';lock<='0';clkn<='0'; --初始化
             next_state<=st1;
   when st1=>cs<='0';a0<='0';rc<='0';lock<='0';clkn<='0'; --启动12位转换
             next_state<=st2;
   when st2=>cs<='0';a0<='0';rc<='0';lock<='0';clkn<='0'; --等待转换
      if status='1' then  next_state<=st2;
        else next_state<=st3;
        end if;
   when st3=>cs<='0';a0<='0';rc<='1';lock<='0';clkn<='1'; --12位并行输出有效
             next_state<=st4;
   when st4=>cs<='0';a0<='0';rc<='1';lock<='1';clkn<='1'; --锁存数据
             next_state<=st0;
   when others=>next_state<=st0; -------其它状态返回初始状态
   end case;
end  process pro;
con:process(clk) --------时序进程     
  begin
    if clk'event and clk='1' then 
      current_state<=next_state;------状态转换
    end if;
end  process con;
output:process(lock) --------数据锁存器进程
 begin
    if lock='1' and lock'event then
      regl<=d;
    end if;
 end  process output;
     q<=regl; ---------数据输出
end one;