yuanlitu.tan.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.300 ns
From           : ad1674status
To             : ad1674ctrl:142|current_state.st2
From Clock     : --
To Clock       : global_clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 19.600 ns
From           : adc0809ctrl:117|current_state.st6
To             : oe
From Clock     : global_clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 9.700 ns
From           : d[3]
To             : adc0809ctrl:117|regl[3]
From Clock     : --
To Clock       : global_clk
Failed Paths   : 0

Type           : Clock Setup: 'global_clk'
Slack          : N/A
Required Time  : None
Actual Time    : 28.57 MHz ( period = 35.000 ns )
From           : adc0809ctrl:117|regl[0]
To             : bio_polor1:137|pwm
From Clock     : global_clk
To Clock       : global_clk
Failed Paths   : 0

Type           : Clock Hold: 'global_clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : ad1674ctrl:143|regl[1]
To             : qiankui:114|reg1[1]
From Clock     : global_clk
To Clock       : global_clk
Failed Paths   : 4

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 4

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