yuanlitu.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "ITDB_TH_RESULT" "adc0809ctrl:117\|regl\[3\] d\[3\] global_clk 9.700 ns register " "Info: th for register \"adc0809ctrl:117\|regl\[3\]\" (data pin = \"d\[3\]\", clock pin = \"global_clk\") is 9.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "global_clk destination 13.700 ns + Longest register " "Info: + Longest clock path from clock \"global_clk\" to destination register is 13.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns global_clk 1 CLK PIN_43 29 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 29; CLK Node = 'global_clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { global_clk } "NODE_NAME" } } { "yuanlitu.bdf" "" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 624 184 352 640 "global_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns fenpinadc0809:130\|fout1 2 REG LC2_C1 9 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC2_C1; Fanout = 9; REG Node = 'fenpinadc0809:130\|fout1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { global_clk fenpinadc0809:130|fout1 } "NODE_NAME" } } { "FENPINADC0809.vhd" "" { Text "D:/my_eda4/fpga_program/FENPINADC0809.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(1.100 ns) 10.700 ns adc0809ctrl:117\|current_state.st6 3 REG LC8_A3 10 " "Info: 3: + IC(3.200 ns) + CELL(1.100 ns) = 10.700 ns; Loc. = LC8_A3; Fanout = 10; REG Node = 'adc0809ctrl:117\|current_state.st6'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.300 ns" { fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 } "NODE_NAME" } } { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(0.000 ns) 13.700 ns adc0809ctrl:117\|regl\[3\] 4 REG LC1_A18 2 " "Info: 4: + IC(3.000 ns) + CELL(0.000 ns) = 13.700 ns; Loc. = LC1_A18; Fanout = 2; REG Node = 'adc0809ctrl:117\|regl\[3\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { adc0809ctrl:117|current_state.st6 adc0809ctrl:117|regl[3] } "NODE_NAME" } } { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 36.50 % ) " "Info: Total cell delay = 5.000 ns ( 36.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.700 ns ( 63.50 % ) " "Info: Total interconnect delay = 8.700 ns ( 63.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.700 ns" { global_clk fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 adc0809ctrl:117|regl[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.700 ns" { global_clk global_clk~out fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 adc0809ctrl:117|regl[3] } { 0.000ns 0.000ns 2.500ns 3.200ns 3.000ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns d\[3\] 1 PIN PIN_1 1 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 1; PIN Node = 'd\[3\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[3] } "NODE_NAME" } } { "yuanlitu.bdf" "" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 832 160 328 848 "d\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.200 ns) 5.600 ns adc0809ctrl:117\|regl\[3\] 2 REG LC1_A18 2 " "Info: 2: + IC(1.600 ns) + CELL(1.200 ns) = 5.600 ns; Loc. = LC1_A18; Fanout = 2; REG Node = 'adc0809ctrl:117\|regl\[3\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { d[3] adc0809ctrl:117|regl[3] } "NODE_NAME" } } { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 71.43 % ) " "Info: Total cell delay = 4.000 ns ( 71.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 28.57 % ) " "Info: Total interconnect delay = 1.600 ns ( 28.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { d[3] adc0809ctrl:117|regl[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { d[3] d[3]~out adc0809ctrl:117|regl[3] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.700 ns" { global_clk fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 adc0809ctrl:117|regl[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.700 ns" { global_clk global_clk~out fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 adc0809ctrl:117|regl[3] } { 0.000ns 0.000ns 2.500ns 3.200ns 3.000ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { d[3] adc0809ctrl:117|regl[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { d[3] d[3]~out adc0809ctrl:117|regl[3] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.200ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "101 " "Info: Allocated 101 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 26 11:13:49 2007 " "Info: Processing ended: Sat May 26 11:13:49 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}