yuanlitu.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "global_clk 4 " "Warning: Circuit may not operate. Detected 4 non-operational path(s) clocked by clock \"global_clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "ad1674ctrl:143\|regl\[1\] qiankui:114\|reg1\[1\] global_clk 2.9 ns " "Info: Found hold time violation between source  pin or register \"ad1674ctrl:143\|regl\[1\]\" and destination pin or register \"qiankui:114\|reg1\[1\]\" for clock \"global_clk\" (Hold time is 2.9 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.200 ns + Largest " "Info: + Largest clock skew is 4.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "global_clk destination 13.100 ns + Longest register " "Info: + Longest clock path from clock \"global_clk\" to destination register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns global_clk 1 CLK PIN_43 29 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 29; CLK Node = 'global_clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { global_clk } "NODE_NAME" } } { "yuanlitu.bdf" "" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 624 184 352 640 "global_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns ad1674ctrl:143\|current_state.st3 2 REG LC8_C24 2 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC8_C24; Fanout = 2; REG Node = 'ad1674ctrl:143\|current_state.st3'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { global_clk ad1674ctrl:143|current_state.st3 } "NODE_NAME" } } { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 9.300 ns ad1674ctrl:143\|clkn 3 COMB LC2_C24 24 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 9.300 ns; Loc. = LC2_C24; Fanout = 24; COMB Node = 'ad1674ctrl:143\|clkn'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { ad1674ctrl:143|current_state.st3 ad1674ctrl:143|clkn } "NODE_NAME" } } { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(0.000 ns) 13.100 ns qiankui:114\|reg1\[1\] 4 REG LC4_C13 5 " "Info: 4: + IC(3.800 ns) + CELL(0.000 ns) = 13.100 ns; Loc. = LC4_C13; Fanout = 5; REG Node = 'qiankui:114\|reg1\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { ad1674ctrl:143|clkn qiankui:114|reg1[1] } "NODE_NAME" } } { "QIANKUI.vhd" "" { Text "D:/my_eda4/fpga_program/QIANKUI.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.200 ns ( 47.33 % ) " "Info: Total cell delay = 6.200 ns ( 47.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns ( 52.67 % ) " "Info: Total interconnect delay = 6.900 ns ( 52.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { global_clk ad1674ctrl:143|current_state.st3 ad1674ctrl:143|clkn qiankui:114|reg1[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { global_clk global_clk~out ad1674ctrl:143|current_state.st3 ad1674ctrl:143|clkn qiankui:114|reg1[1] } { 0.000ns 0.000ns 2.500ns 0.600ns 3.800ns } { 0.000ns 2.800ns 1.100ns 2.300ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "global_clk source 8.900 ns - Shortest register " "Info: - Shortest clock path from clock \"global_clk\" to source register is 8.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns global_clk 1 CLK PIN_43 29 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 29; CLK Node = 'global_clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { global_clk } "NODE_NAME" } } { "yuanlitu.bdf" "" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 624 184 352 640 "global_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns ad1674ctrl:143\|current_state.st4 2 REG LC7_C24 15 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC7_C24; Fanout = 15; REG Node = 'ad1674ctrl:143\|current_state.st4'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { global_clk ad1674ctrl:143|current_state.st4 } "NODE_NAME" } } { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 8.900 ns ad1674ctrl:143\|regl\[1\] 3 REG LC6_C13 8 " "Info: 3: + IC(2.500 ns) + CELL(0.000 ns) = 8.900 ns; Loc. = LC6_C13; Fanout = 8; REG Node = 'ad1674ctrl:143\|regl\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { ad1674ctrl:143|current_state.st4 ad1674ctrl:143|regl[1] } "NODE_NAME" } } { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 43.82 % ) " "Info: Total cell delay = 3.900 ns ( 43.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns ( 56.18 % ) " "Info: Total interconnect delay = 5.000 ns ( 56.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.900 ns" { global_clk ad1674ctrl:143|current_state.st4 ad1674ctrl:143|regl[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.900 ns" { global_clk global_clk~out ad1674ctrl:143|current_state.st4 ad1674ctrl:143|regl[1] } { 0.000ns 0.000ns 2.500ns 2.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { global_clk ad1674ctrl:143|current_state.st3 ad1674ctrl:143|clkn qiankui:114|reg1[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { global_clk global_clk~out ad1674ctrl:143|current_state.st3 ad1674ctrl:143|clkn qiankui:114|reg1[1] } { 0.000ns 0.000ns 2.500ns 0.600ns 3.800ns } { 0.000ns 2.800ns 1.100ns 2.300ns 0.000ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.900 ns" { global_clk ad1674ctrl:143|current_state.st4 ad1674ctrl:143|regl[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.900 ns" { global_clk global_clk~out ad1674ctrl:143|current_state.st4 ad1674ctrl:143|regl[1] } { 0.000ns 0.000ns 2.500ns 2.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 47 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns - Shortest register register " "Info: - Shortest register to register delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ad1674ctrl:143\|regl\[1\] 1 REG LC6_C13 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_C13; Fanout = 8; REG Node = 'ad1674ctrl:143\|regl\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ad1674ctrl:143|regl[1] } "NODE_NAME" } } { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 1.800 ns qiankui:114\|reg1\[1\] 2 REG LC4_C13 5 " "Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC4_C13; Fanout = 5; REG Node = 'qiankui:114\|reg1\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { ad1674ctrl:143|regl[1] qiankui:114|reg1[1] } "NODE_NAME" } } { "QIANKUI.vhd" "" { Text "D:/my_eda4/fpga_program/QIANKUI.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns ( 66.67 % ) " "Info: Total cell delay = 1.200 ns ( 66.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 33.33 % ) " "Info: Total interconnect delay = 0.600 ns ( 33.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { ad1674ctrl:143|regl[1] qiankui:114|reg1[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.800 ns" { ad1674ctrl:143|regl[1] qiankui:114|reg1[1] } { 0.000ns 0.600ns } { 0.000ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "QIANKUI.vhd" "" { Text "D:/my_eda4/fpga_program/QIANKUI.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.100 ns" { global_clk ad1674ctrl:143|current_state.st3 ad1674ctrl:143|clkn qiankui:114|reg1[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.100 ns" { global_clk global_clk~out ad1674ctrl:143|current_state.st3 ad1674ctrl:143|clkn qiankui:114|reg1[1] } { 0.000ns 0.000ns 2.500ns 0.600ns 3.800ns } { 0.000ns 2.800ns 1.100ns 2.300ns 0.000ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.900 ns" { global_clk ad1674ctrl:143|current_state.st4 ad1674ctrl:143|regl[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.900 ns" { global_clk global_clk~out ad1674ctrl:143|current_state.st4 ad1674ctrl:143|regl[1] } { 0.000ns 0.000ns 2.500ns 2.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { ad1674ctrl:143|regl[1] qiankui:114|reg1[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.800 ns" { ad1674ctrl:143|regl[1] qiankui:114|reg1[1] } { 0.000ns 0.600ns } { 0.000ns 1.200ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ad1674ctrl:142\|current_state.st2 ad1674status global_clk 3.300 ns register " "Info: tsu for register \"ad1674ctrl:142\|current_state.st2\" (data pin = \"ad1674status\", clock pin = \"global_clk\") is 3.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Longest pin register " "Info: + Longest pin to register delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns ad1674status 1 PIN PIN_42 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_42; Fanout = 2; PIN Node = 'ad1674status'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ad1674status } "NODE_NAME" } } { "yuanlitu.bdf" "" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 368 176 344 384 "ad1674status" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.700 ns) 6.100 ns ad1674ctrl:142\|current_state.st2 2 REG LC4_B7 3 " "Info: 2: + IC(1.600 ns) + CELL(1.700 ns) = 6.100 ns; Loc. = LC4_B7; Fanout = 3; REG Node = 'ad1674ctrl:142\|current_state.st2'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.300 ns" { ad1674status ad1674ctrl:142|current_state.st2 } "NODE_NAME" } } { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 73.77 % ) " "Info: Total cell delay = 4.500 ns ( 73.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 26.23 % ) " "Info: Total interconnect delay = 1.600 ns ( 26.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { ad1674status ad1674ctrl:142|current_state.st2 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { ad1674status ad1674status~out ad1674ctrl:142|current_state.st2 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "global_clk destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"global_clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns global_clk 1 CLK PIN_43 29 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 29; CLK Node = 'global_clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { global_clk } "NODE_NAME" } } { "yuanlitu.bdf" "" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 624 184 352 640 "global_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns ad1674ctrl:142\|current_state.st2 2 REG LC4_B7 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_B7; Fanout = 3; REG Node = 'ad1674ctrl:142\|current_state.st2'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { global_clk ad1674ctrl:142|current_state.st2 } "NODE_NAME" } } { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { global_clk ad1674ctrl:142|current_state.st2 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { global_clk global_clk~out ad1674ctrl:142|current_state.st2 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { ad1674status ad1674ctrl:142|current_state.st2 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { ad1674status ad1674status~out ad1674ctrl:142|current_state.st2 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { global_clk ad1674ctrl:142|current_state.st2 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { global_clk global_clk~out ad1674ctrl:142|current_state.st2 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "global_clk oe adc0809ctrl:117\|current_state.st6 19.600 ns register " "Info: tco from clock \"global_clk\" to destination pin \"oe\" through register \"adc0809ctrl:117\|current_state.st6\" is 19.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "global_clk source 9.600 ns + Longest register " "Info: + Longest clock path from clock \"global_clk\" to source register is 9.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns global_clk 1 CLK PIN_43 29 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 29; CLK Node = 'global_clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { global_clk } "NODE_NAME" } } { "yuanlitu.bdf" "" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 624 184 352 640 "global_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns fenpinadc0809:130\|fout1 2 REG LC2_C1 9 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC2_C1; Fanout = 9; REG Node = 'fenpinadc0809:130\|fout1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { global_clk fenpinadc0809:130|fout1 } "NODE_NAME" } } { "FENPINADC0809.vhd" "" { Text "D:/my_eda4/fpga_program/FENPINADC0809.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(0.000 ns) 9.600 ns adc0809ctrl:117\|current_state.st6 3 REG LC8_A3 10 " "Info: 3: + IC(3.200 ns) + CELL(0.000 ns) = 9.600 ns; Loc. = LC8_A3; Fanout = 10; REG Node = 'adc0809ctrl:117\|current_state.st6'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 } "NODE_NAME" } } { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 40.63 % ) " "Info: Total cell delay = 3.900 ns ( 40.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.700 ns ( 59.38 % ) " "Info: Total interconnect delay = 5.700 ns ( 59.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.600 ns" { global_clk fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.600 ns" { global_clk global_clk~out fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 } { 0.000ns 0.000ns 2.500ns 3.200ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.900 ns + Longest register pin " "Info: + Longest register to pin delay is 8.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adc0809ctrl:117\|current_state.st6 1 REG LC8_A3 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A3; Fanout = 10; REG Node = 'adc0809ctrl:117\|current_state.st6'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { adc0809ctrl:117|current_state.st6 } "NODE_NAME" } } { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns adc0809ctrl:117\|oe 2 COMB LC6_A3 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC6_A3; Fanout = 1; COMB Node = 'adc0809ctrl:117\|oe'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { adc0809ctrl:117|current_state.st6 adc0809ctrl:117|oe } "NODE_NAME" } } { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(5.100 ns) 8.900 ns oe 3 PIN PIN_7 0 " "Info: 3: + IC(0.900 ns) + CELL(5.100 ns) = 8.900 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'oe'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { adc0809ctrl:117|oe oe } "NODE_NAME" } } { "yuanlitu.bdf" "" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 848 616 792 864 "oe" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns ( 83.15 % ) " "Info: Total cell delay = 7.400 ns ( 83.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 16.85 % ) " "Info: Total interconnect delay = 1.500 ns ( 16.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.900 ns" { adc0809ctrl:117|current_state.st6 adc0809ctrl:117|oe oe } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.900 ns" { adc0809ctrl:117|current_state.st6 adc0809ctrl:117|oe oe } { 0.000ns 0.600ns 0.900ns } { 0.000ns 2.300ns 5.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.600 ns" { global_clk fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.600 ns" { global_clk global_clk~out fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 } { 0.000ns 0.000ns 2.500ns 3.200ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.900 ns" { adc0809ctrl:117|current_state.st6 adc0809ctrl:117|oe oe } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.900 ns" { adc0809ctrl:117|current_state.st6 adc0809ctrl:117|oe oe } { 0.000ns 0.600ns 0.900ns } { 0.000ns 2.300ns 5.100ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}