yuanlitu.smp_dump.txt

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· 文本 代码 · 共 27 行

State Machine - |yuanlitu|ad1674ctrl:143|current_state
Name current_state.st4 current_state.st3 current_state.st2 current_state.st1 current_state.st0 
current_state.st0 0 0 0 0 0 
current_state.st1 0 0 0 1 1 
current_state.st2 0 0 1 0 1 
current_state.st3 0 1 0 0 1 
current_state.st4 1 0 0 0 1 

State Machine - |yuanlitu|ad1674ctrl:142|current_state
Name current_state.st4 current_state.st3 current_state.st2 current_state.st1 current_state.st0 
current_state.st0 0 0 0 0 0 
current_state.st1 0 0 0 1 1 
current_state.st2 0 0 1 0 1 
current_state.st3 0 1 0 0 1 
current_state.st4 1 0 0 0 1 

State Machine - |yuanlitu|adc0809ctrl:117|current_state
Name current_state.st6 current_state.st5 current_state.st4 current_state.st3 current_state.st2 current_state.st1 current_state.st0 
current_state.st0 0 0 0 0 0 0 0 
current_state.st1 0 0 0 0 0 1 1 
current_state.st2 0 0 0 0 1 0 1 
current_state.st3 0 0 0 1 0 0 1 
current_state.st4 0 0 1 0 0 0 1 
current_state.st5 0 1 0 0 0 0 1 
current_state.st6 1 0 0 0 0 0 1