adc0809ctrl.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

--0809控制器
--0809的时钟为500kHz
library ieee;
use ieee.std_logic_1164.all;
entity adc0809ctrl is 
 port(D:in std_logic_vector(7 downto 0);
      clk,eoc:in std_logic;            --状态机时钟和状态信号
      ale,start,oe:out std_logic;      --adc0809控制信号 
      clkn:out std_logic;              --内部锁存信号lock的测试端
      q:out std_logic_vector(7 downto 0)); --锁存数据输出
end;
architecture one of adc0809ctrl is
 type states is (st0,st1,st2,st3,st4,st5,st6);
 signal current_state,next_state:states:=st0; --状态转换及信号控制进程
  signal regl:std_logic_vector(7 downto 0);
  signal lock:std_logic;
begin
pro:process(current_state,eoc) --------状态转换及信号控制进程
  begin 
   case current_state is
   when st0=>ale<='0';start<='0';oe<='0';lock<='0';clkn<='0'; 
        next_state<=st1;                    
   when st1=>ale<='1';start<='0';oe<='0';lock<='0';clkn<='0';-----初始化
        next_state<=st2;
   when st2=>ale<='0';start<='1';oe<='0';lock<='0';clkn<='0';-----启动8位转换
        next_state<=st3;
   when st3=>ale<='0';start<='0';oe<='0';lock<='0';clkn<='0';
        if eoc='1' then  next_state<=st3; ---------等待转换
        else next_state<=st4;
        end if;
   when st4=>ale<='0';start<='0';oe<='0';lock<='0';clkn<='1';
        if eoc='0' then  next_state<=st4;------12位并行输出有效
        else next_state<=st5;
        end if;
   when st5=>ale<='0';start<='0';oe<='1';lock<='0';clkn<='1';
        next_state<=st6;                       --锁存数据
   when st6=>ale<='0';start<='0';oe<='1';lock<='1';clkn<='1';
        next_state<=st0;                       --返回初始状态
   when others=>ale<='0';start<='0';oe<='0';lock<='0';clkn<='0';
        next_state<=st0;                       --其它状态返回初始状态
   end case;
end  process pro;
con:process(clk)------时序进程
  begin
    if clk'event and clk='1' then 
      current_state<=next_state; ------状态转换
    end if;
end  process con;
output:process(lock) -------------数据锁存器进程
 begin
    if lock='1' and lock'event then
      regl<=d;
    end if;
 end  process output;
     q<=regl; ------------------数据输出
end one;