fenpinadc0809.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpinadc0809 is 
 port(
      clk:in std_logic;    ------时钟信号20MhZ
      fout:out std_logic);  -----频率信号输出500KHz       
end;
architecture one of fenpinadc0809 is
signal fout1:std_logic;
begin
process(clk)
variable count:integer range 0 to 19;
begin
if clk'event and clk='1' then 
  if count=19 then 
	 fout1<=not fout1;
	 count:=0;
  else 
     count:=count+1;
  end if;
end if;
end process;
fout<=fout1;
end one;