yuanlitu.fit.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 11 行

Fitter Status : Successful - Sat May 26 11:13:29 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : yuanlitu
Top-level Entity Name : yuanlitu
Family : FLEX10K
Device : EPF10K10LC84-4
Timing Models : Final
Total logic elements : 319 / 576 ( 55 % )
Total pins : 50 / 59 ( 85 % )
Total memory bits : 0 / 6,144 ( 0 % )