yuanlitu.map.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 9 行

Analysis & Synthesis Status : Successful - Sat May 26 11:13:08 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : yuanlitu
Top-level Entity Name : yuanlitu
Family : FLEX10K
Total logic elements : 317
Total pins : 50
Total memory bits : 0