hyperthermia_top.hier_info

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

clk => t[4].CLK
clk => t[5].CLK
clk => t[6].CLK
clk => t[7].CLK
clk => t[8].CLK
clk => t[9].CLK
clk => cont~reg0.CLK
clk => data.CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => count[4].CLK
clk => count[5].CLK
clk => count[6].CLK
clk => num[0].CLK
clk => num[1].CLK
clk => num[2].CLK
clk => num[3].CLK
clk => num[4].CLK
clk => num[5].CLK
clk => num[6].CLK
dq => t~0.DATAB
dq => t~1.DATAB
dq => t~2.DATAB
dq => t~3.DATAB
dq => t~4.DATAB
dq => t~5.DATAB
dq => t~6.DATAB
dq => t~7.DATAB
dq => t~8.DATAB
dq => t~9.DATAB
d <= data.DB_MAX_OUTPUT_PORT_TYPE
cont <= cont~reg0.DB_MAX_OUTPUT_PORT_TYPE
temp[0] <= t[0].DB_MAX_OUTPUT_PORT_TYPE
temp[1] <= t[1].DB_MAX_OUTPUT_PORT_TYPE
temp[2] <= t[2].DB_MAX_OUTPUT_PORT_TYPE
temp[3] <= t[3].DB_MAX_OUTPUT_PORT_TYPE
temp[4] <= t[4].DB_MAX_OUTPUT_PORT_TYPE
temp[5] <= t[5].DB_MAX_OUTPUT_PORT_TYPE
temp[6] <= t[6].DB_MAX_OUTPUT_PORT_TYPE
temp[7] <= t[7].DB_MAX_OUTPUT_PORT_TYPE
temp[8] <= t[8].DB_MAX_OUTPUT_PORT_TYPE
temp[9] <= t[9].DB_MAX_OUTPUT_PORT_TYPE


|Hyperthermia_top|two_dimension_top:inst1
pwm1 <= pwm:inst6.pwm1
clk10kHz => pwm:inst6.clk
clk10kHz => clk_1hz:inst11.clk10k
clk1MHz => lpm_rom0:inst5.clock
specified_temp[0] => add_sub:inst1.dataa[0]
specified_temp[1] => add_sub:inst1.dataa[1]
specified_temp[2] => add_sub:inst1.dataa[2]
specified_temp[3] => add_sub:inst1.dataa[3]
specified_temp[4] => add_sub:inst1.dataa[4]
specified_temp[5] => add_sub:inst1.dataa[5]
specified_temp[6] => add_sub:inst1.dataa[6]
specified_temp[7] => add_sub:inst1.dataa[7]
specified_temp[8] => add_sub:inst1.dataa[8]
specified_temp[9] => add_sub:inst1.dataa[9]
temp[0] => add_sub:inst1.datab[0]
temp[0] => add_sub:inst3.dataa[0]
temp[0] => lpm_dff0:inst2.data[0]
temp[1] => add_sub:inst1.datab[1]
temp[1] => add_sub:inst3.dataa[1]
temp[1] => lpm_dff0:inst2.data[1]
temp[2] => add_sub:inst1.datab[2]
temp[2] => add_sub:inst3.dataa[2]
temp[2] => lpm_dff0:inst2.data[2]
temp[3] => add_sub:inst1.datab[3]
temp[3] => add_sub:inst3.dataa[3]
temp[3] => lpm_dff0:inst2.data[3]
temp[4] => add_sub:inst1.datab[4]
temp[4] => add_sub:inst3.dataa[4]
temp[4] => lpm_dff0:inst2.data[4]
temp[5] => add_sub:inst1.datab[5]
temp[5] => add_sub:inst3.dataa[5]
temp[5] => lpm_dff0:inst2.data[5]
temp[6] => add_sub:inst1.datab[6]
temp[6] => add_sub:inst3.dataa[6]
temp[6] => lpm_dff0:inst2.data[6]
temp[7] => add_sub:inst1.datab[7]
temp[7] => add_sub:inst3.dataa[7]
temp[7] => lpm_dff0:inst2.data[7]
temp[8] => add_sub:inst1.datab[8]
temp[8] => add_sub:inst3.dataa[8]
temp[8] => lpm_dff0:inst2.data[8]
temp[9] => add_sub:inst1.datab[9]
temp[9] => add_sub:inst3.dataa[9]
temp[9] => lpm_dff0:inst2.data[9]
pwm2 <= pwm:inst6.pwm2


|Hyperthermia_top|two_dimension_top:inst1|pwm:inst6
ctrl[0] => LessThan0.IN10
ctrl[0] => LessThan2.IN10
ctrl[0] => LessThan4.IN10
ctrl[1] => LessThan0.IN9
ctrl[1] => LessThan2.IN9
ctrl[1] => Add1.IN8
ctrl[2] => LessThan0.IN8
ctrl[2] => LessThan2.IN8
ctrl[2] => Add1.IN7
ctrl[3] => LessThan0.IN7
ctrl[3] => LessThan2.IN7
ctrl[3] => Add1.IN6
clk => pwm2~reg0.CLK
clk => pwm1~reg0.CLK
clk => cnt[0].CLK
clk => cnt[1].CLK
clk => cnt[2].CLK
clk => cnt[3].CLK
clk => cnt[4].CLK
pwm1 <= pwm1~reg0.DB_MAX_OUTPUT_PORT_TYPE
pwm2 <= pwm2~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Hyperthermia_top|two_dimension_top:inst1|lpm_rom0:inst5
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]


|Hyperthermia_top|two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_p971:auto_generated.address_a[0]
address_a[1] => altsyncram_p971:auto_generated.address_a[1]
address_a[2] => altsyncram_p971:auto_generated.address_a[2]
address_a[3] => altsyncram_p971:auto_generated.address_a[3]
address_a[4] => altsyncram_p971:auto_generated.address_a[4]
address_a[5] => altsyncram_p971:auto_generated.address_a[5]
address_a[6] => altsyncram_p971:auto_generated.address_a[6]
address_a[7] => altsyncram_p971:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_p971:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_p971:auto_generated.q_a[0]
q_a[1] <= altsyncram_p971:auto_generated.q_a[1]
q_a[2] <= altsyncram_p971:auto_generated.q_a[2]
q_a[3] <= altsyncram_p971:auto_generated.q_a[3]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|Hyperthermia_top|two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component|altsyncram_p971:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT


|Hyperthermia_top|two_dimension_top:inst1|two_dimension_fuzzy:inst
t_error[0] => LessThan0.IN20
t_error[0] => LessThan1.IN20
t_error[0] => LessThan2.IN20
t_error[0] => LessThan3.IN20
t_error[0] => LessThan4.IN20
t_error[0] => LessThan5.IN20
t_error[0] => LessThan6.IN20
t_error[0] => LessThan7.IN20
t_error[0] => LessThan8.IN20
t_error[0] => LessThan9.IN20
t_error[0] => LessThan10.IN20
t_error[0] => LessThan11.IN20
t_error[0] => LessThan12.IN20
t_error[0] => LessThan13.IN20
t_error[0] => LessThan14.IN20
t_error[0] => Equal0.IN19
t_error[1] => LessThan0.IN19
t_error[1] => LessThan1.IN19
t_error[1] => LessThan2.IN19
t_error[1] => LessThan3.IN19
t_error[1] => LessThan4.IN19
t_error[1] => LessThan5.IN19
t_error[1] => LessThan6.IN19
t_error[1] => LessThan7.IN19
t_error[1] => LessThan8.IN19
t_error[1] => LessThan9.IN19
t_error[1] => LessThan10.IN19
t_error[1] => LessThan11.IN19
t_error[1] => LessThan12.IN19
t_error[1] => LessThan13.IN19
t_error[1] => LessThan14.IN19
t_error[1] => Equal0.IN18
t_error[2] => LessThan0.IN18
t_error[2] => LessThan1.IN18
t_error[2] => LessThan2.IN18
t_error[2] => LessThan3.IN18
t_error[2] => LessThan4.IN18
t_error[2] => LessThan5.IN18
t_error[2] => LessThan6.IN18
t_error[2] => LessThan7.IN18
t_error[2] => LessThan8.IN18
t_error[2] => LessThan9.IN18
t_error[2] => LessThan10.IN18
t_error[2] => LessThan11.IN18
t_error[2] => LessThan12.IN18
t_error[2] => LessThan13.IN18
t_error[2] => LessThan14.IN18
t_error[2] => Equal0.IN17
t_error[3] => LessThan0.IN17
t_error[3] => LessThan1.IN17
t_error[3] => LessThan2.IN17
t_error[3] => LessThan3.IN17
t_error[3] => LessThan4.IN17
t_error[3] => LessThan5.IN17
t_error[3] => LessThan6.IN17
t_error[3] => LessThan7.IN17
t_error[3] => LessThan8.IN17
t_error[3] => LessThan9.IN17
t_error[3] => LessThan10.IN17
t_error[3] => LessThan11.IN17
t_error[3] => LessThan12.IN17
t_error[3] => LessThan13.IN17
t_error[3] => LessThan14.IN17
t_error[3] => Equal0.IN16
t_error[4] => LessThan0.IN16
t_error[4] => LessThan1.IN16
t_error[4] => LessThan2.IN16
t_error[4] => LessThan3.IN16
t_error[4] => LessThan4.IN16
t_error[4] => LessThan5.IN16
t_error[4] => LessThan6.IN16
t_error[4] => LessThan7.IN16
t_error[4] => LessThan8.IN16
t_error[4] => LessThan9.IN16
t_error[4] => LessThan10.IN16
t_error[4] => LessThan11.IN16
t_error[4] => LessThan12.IN16
t_error[4] => LessThan13.IN16
t_error[4] => LessThan14.IN16
t_error[4] => Equal0.IN15
t_error[5] => LessThan0.IN15
t_error[5] => LessThan1.IN15
t_error[5] => LessThan2.IN15
t_error[5] => LessThan3.IN15
t_error[5] => LessThan4.IN15
t_error[5] => LessThan5.IN15
t_error[5] => LessThan6.IN15
t_error[5] => LessThan7.IN15
t_error[5] => LessThan8.IN15
t_error[5] => LessThan9.IN15
t_error[5] => LessThan10.IN15
t_error[5] => LessThan11.IN15
t_error[5] => LessThan12.IN15
t_error[5] => LessThan13.IN15
t_error[5] => LessThan14.IN15
t_error[5] => Equal0.IN14
t_error[6] => LessThan0.IN14
t_error[6] => LessThan1.IN14
t_error[6] => LessThan2.IN14
t_error[6] => LessThan3.IN14
t_error[6] => LessThan4.IN14
t_error[6] => LessThan5.IN14
t_error[6] => LessThan6.IN14
t_error[6] => LessThan7.IN14
t_error[6] => LessThan8.IN14
t_error[6] => LessThan9.IN14
t_error[6] => LessThan10.IN14
t_error[6] => LessThan11.IN14
t_error[6] => LessThan12.IN14
t_error[6] => LessThan13.IN14
t_error[6] => LessThan14.IN14
t_error[6] => Equal0.IN13
t_error[7] => LessThan0.IN13
t_error[7] => LessThan1.IN13
t_error[7] => LessThan2.IN13
t_error[7] => LessThan3.IN13
t_error[7] => LessThan4.IN13
t_error[7] => LessThan5.IN13
t_error[7] => LessThan6.IN13
t_error[7] => LessThan7.IN13
t_error[7] => LessThan8.IN13
t_error[7] => LessThan9.IN13
t_error[7] => LessThan10.IN13
t_error[7] => LessThan11.IN13
t_error[7] => LessThan12.IN13
t_error[7] => LessThan13.IN13
t_error[7] => LessThan14.IN13
t_error[7] => Equal0.IN12
t_error[8] => LessThan0.IN12
t_error[8] => LessThan1.IN12
t_error[8] => LessThan2.IN12
t_error[8] => LessThan3.IN12
t_error[8] => LessThan4.IN12
t_error[8] => LessThan5.IN12
t_error[8] => LessThan6.IN12
t_error[8] => LessThan7.IN12
t_error[8] => LessThan8.IN12
t_error[8] => LessThan9.IN12
t_error[8] => LessThan10.IN12
t_error[8] => LessThan11.IN12
t_error[8] => LessThan12.IN12
t_error[8] => LessThan13.IN12
t_error[8] => LessThan14.IN12
t_error[8] => Equal0.IN11
t_error[9] => LessThan0.IN11
t_error[9] => LessThan1.IN11
t_error[9] => LessThan2.IN11
t_error[9] => LessThan3.IN11
t_error[9] => LessThan4.IN11
t_error[9] => LessThan5.IN11
t_error[9] => LessThan6.IN11
t_error[9] => LessThan7.IN11
t_error[9] => LessThan8.IN11
t_error[9] => LessThan9.IN11
t_error[9] => LessThan10.IN11
t_error[9] => LessThan11.IN11
t_error[9] => LessThan12.IN11
t_error[9] => LessThan13.IN11
t_error[9] => LessThan14.IN11
t_error[9] => Equal0.IN10
flag_e => comb~53.IN0
flag_e => comb~54.OUTPUTSELECT
flag_e => comb~43.OUTPUTSELECT
flag_e => comb~36.OUTPUTSELECT
flag_e => comb~27.OUTPUTSELECT
t_rate[0] => LessThan15.IN20
t_rate[0] => LessThan16.IN20
t_rate[0] => LessThan17.IN20
t_rate[0] => LessThan18.IN20
t_rate[0] => LessThan19.IN20
t_rate[0] => LessThan20.IN20
t_rate[0] => Equal1.IN19
t_rate[0] => Add0.IN11
t_rate[1] => LessThan15.IN19
t_rate[1] => LessThan16.IN19
t_rate[1] => LessThan17.IN19
t_rate[1] => LessThan18.IN19
t_rate[1] => LessThan19.IN19
t_rate[1] => LessThan20.IN19