hyperthermia_top.hier_info

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

|Hyperthermia_top
dot <= display:inst4.dot
show_set => display:inst4.show_set
clk_20M => clk_div:inst.clk20M
rise => sepcified_temp_top:inst2.Rise
down => sepcified_temp_top:inst2.Down
set => sepcified_temp_top:inst2.set
dq <= temperature_top:inst7.dq
signal1 <= inst10.DB_MAX_OUTPUT_PORT_TYPE
ntri => inst10.OE
ntri => inst11.OE
signal2 <= inst11.DB_MAX_OUTPUT_PORT_TYPE
deci_one[0] <= display:inst4.deci_one[0]
deci_one[1] <= display:inst4.deci_one[1]
deci_one[2] <= display:inst4.deci_one[2]
deci_one[3] <= display:inst4.deci_one[3]
deci_one[4] <= display:inst4.deci_one[4]
deci_one[5] <= display:inst4.deci_one[5]
deci_one[6] <= display:inst4.deci_one[6]
deci_ten[0] <= display:inst4.deci_ten[0]
deci_ten[1] <= display:inst4.deci_ten[1]
deci_ten[2] <= display:inst4.deci_ten[2]
deci_ten[3] <= display:inst4.deci_ten[3]
deci_ten[4] <= display:inst4.deci_ten[4]
deci_ten[5] <= display:inst4.deci_ten[5]
deci_ten[6] <= display:inst4.deci_ten[6]
inte_one[0] <= display:inst4.inte_one[0]
inte_one[1] <= display:inst4.inte_one[1]
inte_one[2] <= display:inst4.inte_one[2]
inte_one[3] <= display:inst4.inte_one[3]
inte_one[4] <= display:inst4.inte_one[4]
inte_one[5] <= display:inst4.inte_one[5]
inte_one[6] <= display:inst4.inte_one[6]
inte_ten[0] <= display:inst4.inte_ten[0]
inte_ten[1] <= display:inst4.inte_ten[1]
inte_ten[2] <= display:inst4.inte_ten[2]
inte_ten[3] <= display:inst4.inte_ten[3]
inte_ten[4] <= display:inst4.inte_ten[4]
inte_ten[5] <= display:inst4.inte_ten[5]
inte_ten[6] <= display:inst4.inte_ten[6]


|Hyperthermia_top|display:inst4
dot <= two_to_ten:inst.dot
show_set => two_to_ten:inst.show_set
specified_temp[0] => two_to_ten:inst.specified_temp[0]
specified_temp[1] => two_to_ten:inst.specified_temp[1]
specified_temp[2] => two_to_ten:inst.specified_temp[2]
specified_temp[3] => two_to_ten:inst.specified_temp[3]
specified_temp[4] => two_to_ten:inst.specified_temp[4]
specified_temp[5] => two_to_ten:inst.specified_temp[5]
specified_temp[6] => two_to_ten:inst.specified_temp[6]
specified_temp[7] => two_to_ten:inst.specified_temp[7]
specified_temp[8] => two_to_ten:inst.specified_temp[8]
specified_temp[9] => two_to_ten:inst.specified_temp[9]
temp[0] => two_to_ten:inst.temp[0]
temp[1] => two_to_ten:inst.temp[1]
temp[2] => two_to_ten:inst.temp[2]
temp[3] => two_to_ten:inst.temp[3]
temp[4] => two_to_ten:inst.temp[4]
temp[5] => two_to_ten:inst.temp[5]
temp[6] => two_to_ten:inst.temp[6]
temp[7] => two_to_ten:inst.temp[7]
temp[8] => two_to_ten:inst.temp[8]
temp[9] => two_to_ten:inst.temp[9]
deci_one[0] <= seven:inst4.y[0]
deci_one[1] <= seven:inst4.y[1]
deci_one[2] <= seven:inst4.y[2]
deci_one[3] <= seven:inst4.y[3]
deci_one[4] <= seven:inst4.y[4]
deci_one[5] <= seven:inst4.y[5]
deci_one[6] <= seven:inst4.y[6]
deci_ten[0] <= seven:inst3.y[0]
deci_ten[1] <= seven:inst3.y[1]
deci_ten[2] <= seven:inst3.y[2]
deci_ten[3] <= seven:inst3.y[3]
deci_ten[4] <= seven:inst3.y[4]
deci_ten[5] <= seven:inst3.y[5]
deci_ten[6] <= seven:inst3.y[6]
inte_one[0] <= seven:inst2.y[0]
inte_one[1] <= seven:inst2.y[1]
inte_one[2] <= seven:inst2.y[2]
inte_one[3] <= seven:inst2.y[3]
inte_one[4] <= seven:inst2.y[4]
inte_one[5] <= seven:inst2.y[5]
inte_one[6] <= seven:inst2.y[6]
inte_ten[0] <= seven:inst1.y[0]
inte_ten[1] <= seven:inst1.y[1]
inte_ten[2] <= seven:inst1.y[2]
inte_ten[3] <= seven:inst1.y[3]
inte_ten[4] <= seven:inst1.y[4]
inte_ten[5] <= seven:inst1.y[5]
inte_ten[6] <= seven:inst1.y[6]


|Hyperthermia_top|display:inst4|two_to_ten:inst
specified_temp[0] => t[0].DATAB
specified_temp[1] => t[1].DATAB
specified_temp[2] => t[2].DATAB
specified_temp[3] => t[3].DATAB
specified_temp[4] => t[4].DATAB
specified_temp[5] => t[5].DATAB
specified_temp[6] => t[6].DATAB
specified_temp[7] => t[7].DATAB
specified_temp[8] => t[8].DATAB
specified_temp[9] => t[9].DATAB
temp[0] => t[0].DATAA
temp[1] => t[1].DATAA
temp[2] => t[2].DATAA
temp[3] => t[3].DATAA
temp[4] => t[4].DATAA
temp[5] => t[5].DATAA
temp[6] => t[6].DATAA
temp[7] => t[7].DATAA
temp[8] => t[8].DATAA
temp[9] => t[9].DATAA
show_set => t[9].OUTPUTSELECT
show_set => t[8].OUTPUTSELECT
show_set => t[7].OUTPUTSELECT
show_set => t[6].OUTPUTSELECT
show_set => t[5].OUTPUTSELECT
show_set => t[4].OUTPUTSELECT
show_set => t[3].OUTPUTSELECT
show_set => t[2].OUTPUTSELECT
show_set => t[1].OUTPUTSELECT
show_set => t[0].OUTPUTSELECT
inte_ten[0] <= inte_ten~7.DB_MAX_OUTPUT_PORT_TYPE
inte_ten[1] <= inte_ten~6.DB_MAX_OUTPUT_PORT_TYPE
inte_ten[2] <= inte_ten~5.DB_MAX_OUTPUT_PORT_TYPE
inte_ten[3] <= <GND>
inte_one[0] <= inte_one[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
inte_one[1] <= inte_one[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
inte_one[2] <= inte_one[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
inte_one[3] <= inte_one[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
deci_ten[0] <= deci_ten~16.DB_MAX_OUTPUT_PORT_TYPE
deci_ten[1] <= deci_ten~15.DB_MAX_OUTPUT_PORT_TYPE
deci_ten[2] <= deci_ten~14.DB_MAX_OUTPUT_PORT_TYPE
deci_ten[3] <= deci_ten~13.DB_MAX_OUTPUT_PORT_TYPE
deci_one[0] <= deci_one~5.DB_MAX_OUTPUT_PORT_TYPE
deci_one[1] <= deci_one~4.DB_MAX_OUTPUT_PORT_TYPE
deci_one[2] <= deci_one~3.DB_MAX_OUTPUT_PORT_TYPE
deci_one[3] <= deci_one~2.DB_MAX_OUTPUT_PORT_TYPE
dot <= <VCC>


|Hyperthermia_top|display:inst4|seven:inst4
i[0] => Mux0.IN19
i[0] => Mux1.IN19
i[0] => Mux2.IN19
i[0] => Mux3.IN19
i[0] => Mux4.IN19
i[0] => Mux5.IN19
i[0] => Mux6.IN19
i[1] => Mux0.IN18
i[1] => Mux1.IN18
i[1] => Mux2.IN18
i[1] => Mux3.IN18
i[1] => Mux4.IN18
i[1] => Mux5.IN18
i[1] => Mux6.IN18
i[2] => Mux0.IN17
i[2] => Mux1.IN17
i[2] => Mux2.IN17
i[2] => Mux3.IN17
i[2] => Mux4.IN17
i[2] => Mux5.IN17
i[2] => Mux6.IN17
i[3] => Mux0.IN16
i[3] => Mux1.IN16
i[3] => Mux2.IN16
i[3] => Mux3.IN16
i[3] => Mux4.IN16
i[3] => Mux5.IN16
i[3] => Mux6.IN16
y[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
y[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
y[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
y[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
y[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
y[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
y[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|Hyperthermia_top|display:inst4|seven:inst3
i[0] => Mux0.IN19
i[0] => Mux1.IN19
i[0] => Mux2.IN19
i[0] => Mux3.IN19
i[0] => Mux4.IN19
i[0] => Mux5.IN19
i[0] => Mux6.IN19
i[1] => Mux0.IN18
i[1] => Mux1.IN18
i[1] => Mux2.IN18
i[1] => Mux3.IN18
i[1] => Mux4.IN18
i[1] => Mux5.IN18
i[1] => Mux6.IN18
i[2] => Mux0.IN17
i[2] => Mux1.IN17
i[2] => Mux2.IN17
i[2] => Mux3.IN17
i[2] => Mux4.IN17
i[2] => Mux5.IN17
i[2] => Mux6.IN17
i[3] => Mux0.IN16
i[3] => Mux1.IN16
i[3] => Mux2.IN16
i[3] => Mux3.IN16
i[3] => Mux4.IN16
i[3] => Mux5.IN16
i[3] => Mux6.IN16
y[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
y[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
y[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
y[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
y[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
y[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
y[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|Hyperthermia_top|display:inst4|seven:inst2
i[0] => Mux0.IN19
i[0] => Mux1.IN19
i[0] => Mux2.IN19
i[0] => Mux3.IN19
i[0] => Mux4.IN19
i[0] => Mux5.IN19
i[0] => Mux6.IN19
i[1] => Mux0.IN18
i[1] => Mux1.IN18
i[1] => Mux2.IN18
i[1] => Mux3.IN18
i[1] => Mux4.IN18
i[1] => Mux5.IN18
i[1] => Mux6.IN18
i[2] => Mux0.IN17
i[2] => Mux1.IN17
i[2] => Mux2.IN17
i[2] => Mux3.IN17
i[2] => Mux4.IN17
i[2] => Mux5.IN17
i[2] => Mux6.IN17
i[3] => Mux0.IN16
i[3] => Mux1.IN16
i[3] => Mux2.IN16
i[3] => Mux3.IN16
i[3] => Mux4.IN16
i[3] => Mux5.IN16
i[3] => Mux6.IN16
y[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
y[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
y[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
y[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
y[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
y[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
y[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|Hyperthermia_top|display:inst4|seven:inst1
i[0] => Mux0.IN19
i[0] => Mux1.IN19
i[0] => Mux2.IN19
i[0] => Mux3.IN19
i[0] => Mux4.IN19
i[0] => Mux5.IN19
i[0] => Mux6.IN19
i[1] => Mux0.IN18
i[1] => Mux1.IN18
i[1] => Mux2.IN18
i[1] => Mux3.IN18
i[1] => Mux4.IN18
i[1] => Mux5.IN18
i[1] => Mux6.IN18
i[2] => Mux0.IN17
i[2] => Mux1.IN17
i[2] => Mux2.IN17
i[2] => Mux3.IN17
i[2] => Mux4.IN17
i[2] => Mux5.IN17
i[2] => Mux6.IN17
i[3] => Mux0.IN16
i[3] => Mux1.IN16
i[3] => Mux2.IN16
i[3] => Mux3.IN16
i[3] => Mux4.IN16
i[3] => Mux5.IN16
i[3] => Mux6.IN16
y[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
y[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
y[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
y[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
y[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
y[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
y[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|Hyperthermia_top|sepcified_temp_top:inst2
specified_temp[0] <= specified_temp:inst.specified_temp[0]
specified_temp[1] <= specified_temp:inst.specified_temp[1]
specified_temp[2] <= specified_temp:inst.specified_temp[2]
specified_temp[3] <= specified_temp:inst.specified_temp[3]
specified_temp[4] <= specified_temp:inst.specified_temp[4]
specified_temp[5] <= specified_temp:inst.specified_temp[5]
specified_temp[6] <= specified_temp:inst.specified_temp[6]
specified_temp[7] <= specified_temp:inst.specified_temp[7]
specified_temp[8] <= specified_temp:inst.specified_temp[8]
specified_temp[9] <= specified_temp:inst.specified_temp[9]
Rise => debounce:inst4.key_press
clk100 => debounce:inst4.clk100
clk100 => debounce:inst5.clk100
Down => debounce:inst5.key_press
set => specified_temp:inst.set


|Hyperthermia_top|sepcified_temp_top:inst2|specified_temp:inst
rise => num_rise[0].CLK
rise => num_rise[1].CLK
rise => num_rise[2].CLK
rise => num_rise[3].CLK
down => num_down[0].CLK
down => num_down[1].CLK
down => num_down[2].CLK
down => num_down[3].CLK
set => temp[5].LATCH_ENABLE
set => temp[6].LATCH_ENABLE
set => temp[7].LATCH_ENABLE
set => temp[8].LATCH_ENABLE
set => temp[9].LATCH_ENABLE
set => temp[4].LATCH_ENABLE
set => temp[2].LATCH_ENABLE
set => temp[3].LATCH_ENABLE
set => temp[1].LATCH_ENABLE
set => temp[0].LATCH_ENABLE
specified_temp[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
specified_temp[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
specified_temp[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE
specified_temp[3] <= temp[3].DB_MAX_OUTPUT_PORT_TYPE
specified_temp[4] <= temp[4].DB_MAX_OUTPUT_PORT_TYPE
specified_temp[5] <= temp[5].DB_MAX_OUTPUT_PORT_TYPE
specified_temp[6] <= temp[6].DB_MAX_OUTPUT_PORT_TYPE
specified_temp[7] <= temp[7].DB_MAX_OUTPUT_PORT_TYPE
specified_temp[8] <= temp[8].DB_MAX_OUTPUT_PORT_TYPE
specified_temp[9] <= temp[9].DB_MAX_OUTPUT_PORT_TYPE


|Hyperthermia_top|sepcified_temp_top:inst2|debounce:inst4
singal_pulse <= inst10.DB_MAX_OUTPUT_PORT_TYPE
clk100 => D4.CLK
clk100 => D1.CLK
clk100 => D2.CLK
clk100 => D3.CLK
clk100 => D5.CLK
key_press => D1.DATAIN


|Hyperthermia_top|sepcified_temp_top:inst2|debounce:inst5
singal_pulse <= inst10.DB_MAX_OUTPUT_PORT_TYPE
clk100 => D4.CLK
clk100 => D1.CLK
clk100 => D2.CLK
clk100 => D3.CLK
clk100 => D5.CLK
key_press => D1.DATAIN


|Hyperthermia_top|clk_div:inst
clk20M => clk1M_1.CLK
clk20M => count[0].CLK
clk20M => count[1].CLK
clk20M => count[2].CLK
clk20M => count[3].CLK
clk500k <= clk500k_1.DB_MAX_OUTPUT_PORT_TYPE
clk1M <= clk1M_1.DB_MAX_OUTPUT_PORT_TYPE
clk10k <= clk10k_1.DB_MAX_OUTPUT_PORT_TYPE
clk100 <= clk100_1.DB_MAX_OUTPUT_PORT_TYPE


|Hyperthermia_top|temperature_top:inst7
dq <= inst2
clk_1MHz => temperature:inst.clk
temp[0] <= temperature:inst.temp[0]
temp[1] <= temperature:inst.temp[1]
temp[2] <= temperature:inst.temp[2]
temp[3] <= temperature:inst.temp[3]
temp[4] <= temperature:inst.temp[4]
temp[5] <= temperature:inst.temp[5]
temp[6] <= temperature:inst.temp[6]
temp[7] <= temperature:inst.temp[7]
temp[8] <= temperature:inst.temp[8]
temp[9] <= temperature:inst.temp[9]


|Hyperthermia_top|temperature_top:inst7|temperature:inst
clk => t[0].CLK
clk => t[1].CLK
clk => t[2].CLK
clk => t[3].CLK