hyperthermia_top.map.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Warning: Using design file specified_temp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: specified_temp-behav
    Info: Found entity 1: specified_temp
Info: Elaborating entity "specified_temp" for hierarchy "sepcified_temp_top:inst2|specified_temp:inst"
Warning (10631): VHDL Process Statement warning at specified_temp.vhd(38): inferring latch(es) for signal or variable "temp", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at specified_temp.vhd(38): inferred latch for "temp[0]"
Info (10041): Verilog HDL or VHDL info at specified_temp.vhd(38): inferred latch for "temp[1]"
Info (10041): Verilog HDL or VHDL info at specified_temp.vhd(38): inferred latch for "temp[2]"
Info (10041): Verilog HDL or VHDL info at specified_temp.vhd(38): inferred latch for "temp[3]"
Info (10041): Verilog HDL or VHDL info at specified_temp.vhd(38): inferred latch for "temp[4]"
Info (10041): Verilog HDL or VHDL info at specified_temp.vhd(38): inferred latch for "temp[5]"
Info (10041): Verilog HDL or VHDL info at specified_temp.vhd(38): inferred latch for "temp[6]"
Info (10041): Verilog HDL or VHDL info at specified_temp.vhd(38): inferred latch for "temp[7]"
Info (10041): Verilog HDL or VHDL info at specified_temp.vhd(38): inferred latch for "temp[8]"
Info (10041): Verilog HDL or VHDL info at specified_temp.vhd(38): inferred latch for "temp[9]"
Info: Elaborating entity "debounce" for hierarchy "sepcified_temp_top:inst2|debounce:inst4"
Warning: Using design file clk_div.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: clk_div-one
    Info: Found entity 1: clk_div
Info: Elaborating entity "clk_div" for hierarchy "clk_div:inst"
Warning: Using design file temperature_top.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: temperature_top
Info: Elaborating entity "temperature_top" for hierarchy "temperature_top:inst7"
Warning: Using design file temperature.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: temperature-behav
    Info: Found entity 1: temperature
Info: Elaborating entity "temperature" for hierarchy "temperature_top:inst7|temperature:inst"
Warning: Using design file two_dimension_top.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: two_dimension_top
Info: Elaborating entity "two_dimension_top" for hierarchy "two_dimension_top:inst1"
Warning: Using design file pwm.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: pwm-one
    Info: Found entity 1: pwm
Info: Elaborating entity "pwm" for hierarchy "two_dimension_top:inst1|pwm:inst6"
Warning: Using design file lpm_rom0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_rom0-SYN
    Info: Found entity 1: lpm_rom0
Info: Elaborating entity "lpm_rom0" for hierarchy "two_dimension_top:inst1|lpm_rom0:inst5"
Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_p971.tdf
    Info: Found entity 1: altsyncram_p971
Info: Elaborating entity "altsyncram_p971" for hierarchy "two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component|altsyncram_p971:auto_generated"
Warning: Using design file two_dimension_fuzzy.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: two_dimension_fuzzy-one
    Info: Found entity 1: two_dimension_fuzzy
Info: Elaborating entity "two_dimension_fuzzy" for hierarchy "two_dimension_top:inst1|two_dimension_fuzzy:inst"
Warning (10631): VHDL Process Statement warning at two_dimension_fuzzy.vhd(19): inferring latch(es) for signal or variable "e", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at two_dimension_fuzzy.vhd(47): inferring latch(es) for signal or variable "rt", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at two_dimension_fuzzy.vhd(47): inferring latch(es) for signal or variable "t_rate_n", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "t_rate_n[0]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "t_rate_n[1]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "t_rate_n[2]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "t_rate_n[3]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "t_rate_n[4]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "t_rate_n[5]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "t_rate_n[6]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "t_rate_n[7]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "t_rate_n[8]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "t_rate_n[9]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "rt[0]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "rt[1]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "rt[2]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(47): inferred latch for "rt[3]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(19): inferred latch for "e[0]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(19): inferred latch for "e[1]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(19): inferred latch for "e[2]"
Info (10041): Verilog HDL or VHDL info at two_dimension_fuzzy.vhd(19): inferred latch for "e[3]"
Warning: Using design file add_sub.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: add_sub-SYN
    Info: Found entity 1: add_sub
Info: Elaborating entity "add_sub" for hierarchy "two_dimension_top:inst1|add_sub:inst1"
Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborating entity "lpm_add_sub" for hierarchy "two_dimension_top:inst1|add_sub:inst1|lpm_add_sub:lpm_add_sub_component"
Info: Elaborated megafunction instantiation "two_dimension_top:inst1|add_sub:inst1|lpm_add_sub:lpm_add_sub_component"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_ijf.tdf
    Info: Found entity 1: add_sub_ijf
Info: Elaborating entity "add_sub_ijf" for hierarchy "two_dimension_top:inst1|add_sub:inst1|lpm_add_sub:lpm_add_sub_component|add_sub_ijf:auto_generated"
Warning: Using design file lpm_dff0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_dff0-SYN
    Info: Found entity 1: lpm_dff0
Info: Elaborating entity "lpm_dff0" for hierarchy "two_dimension_top:inst1|lpm_dff0:inst2"
Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/lpm_ff.tdf
    Info: Found entity 1: lpm_ff
Info: Elaborating entity "lpm_ff" for hierarchy "two_dimension_top:inst1|lpm_dff0:inst2|lpm_ff:lpm_ff_component"
Info: Elaborated megafunction instantiation "two_dimension_top:inst1|lpm_dff0:inst2|lpm_ff:lpm_ff_component"
Warning: Using design file clk_1hz.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: clk_1hz-one
    Info: Found entity 1: clk_1hz
Info: Elaborating entity "clk_1hz" for hierarchy "two_dimension_top:inst1|clk_1hz:inst11"
Info: Duplicate registers merged to single register
    Info: Duplicate register "clk_div:inst|\process4:count[0]" merged to single register "two_dimension_top:inst1|pwm:inst6|cnt[0]"
    Info: Duplicate register "two_dimension_top:inst1|clk_1hz:inst11|count[0]" merged to single register "two_dimension_top:inst1|pwm:inst6|cnt[0]"
    Info: Duplicate register "two_dimension_top:inst1|clk_1hz:inst11|count[1]" merged to single register "two_dimension_top:inst1|pwm:inst6|cnt[1]"
Warning: Latch display:inst4|two_to_ten:inst|inte_one[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal temperature_top:inst7|temperature:inst|t[4]
Warning: Latch display:inst4|two_to_ten:inst|inte_one[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal temperature_top:inst7|temperature:inst|t[5]
Warning: Latch display:inst4|two_to_ten:inst|inte_one[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal temperature_top:inst7|temperature:inst|t[6]
Warning: Latch display:inst4|two_to_ten:inst|inte_one[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal temperature_top:inst7|temperature:inst|t[9]
Warning: Latch two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal two_dimension_top:inst1|two_dimension_fuzzy:inst|t_rate_n[9]
Warning: Latch two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal two_dimension_top:inst1|two_dimension_fuzzy:inst|t_rate_n[9]
Warning: Latch two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal two_dimension_top:inst1|add_sub:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_ijf:auto_generated|op_1~152
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "dot" stuck at VCC
    Warning: Pin "deci_one[4]" stuck at VCC
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 42 warnings
    Info: Allocated 154 megabytes of memory during processing
    Info: Processing ended: Wed May 30 10:54:46 2007
    Info: Elapsed time: 00:00:25