rom_data.mif

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

-- Copyright (C) 1991-2007 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- Quartus II generated Memory Initialization File (.mif)

WIDTH=4;
DEPTH=256;

ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;

CONTENT BEGIN
	000  :   3;
	001  :   2;
	[002..00F]  :   0;
	010  :   4;
	011  :   3;
	012  :   2;
	[013..01F]  :   0;
	020  :   5;
	021  :   4;
	022  :   3;
	023  :   2;
	024  :   1;
	[025..02F]  :   0;
	030  :   6;
	031  :   5;
	032  :   4;
	033  :   3;
	034  :   2;
	035  :   1;
	[036..03F]  :   0;
	040  :   7;
	041  :   6;
	042  :   5;
	043  :   4;
	044  :   3;
	045  :   2;
	046  :   1;
	[047..04F]  :   0;
	050  :   8;
	051  :   7;
	052  :   6;
	053  :   5;
	054  :   4;
	055  :   3;
	056  :   2;
	057  :   1;
	[058..05F]  :   0;
	[060..061]  :   8;
	062  :   7;
	063  :   6;
	064  :   5;
	065  :   4;
	066  :   3;
	067  :   2;
	068  :   1;
	[069..06F]  :   0;
	[070..072]  :   8;
	073  :   7;
	074  :   6;
	075  :   5;
	076  :   4;
	077  :   3;
	078  :   2;
	[079..07F]  :   0;
	[080..083]  :   8;
	084  :   7;
	085  :   6;
	086  :   5;
	087  :   4;
	088  :   3;
	[089..08F]  :   0;
	[090..094]  :   8;
	095  :   7;
	096  :   6;
	097  :   5;
	098  :   4;
	[099..0FF]  :   0;
END;