sel.v

EDA 数字钟实现文件 能够实现计时,闹钟,校时功能

module sel (clksp,secl,sech,minl,minh,hourl,hourh,Display,sel);
 input clksp;
 input [3:0] secl;
 input [3:0] sech;
 input [3:0] minl;
 input [3:0] minh;
 input [3:0] hourl;
 input [1:0] hourh;
 output [6:0] Display;
 output [2:0] sel;
 reg [6:0] Display;
 reg [3:0] Disp_Temp;
 reg [2:0] sel;


always @ (posedge clksp)
begin
  sel <= sel+1; 
end

always @ (sel)
begin
case(sel)
3'b111: Disp_Temp=hourh;
3'b110: Disp_Temp=hourl;
3'b101: Disp_Temp=4'b1010;
3'b100: Disp_Temp=minh;
3'b011: Disp_Temp=minl;
3'b010: Disp_Temp=4'b1010;
3'b001: Disp_Temp=sech;
3'b000: Disp_Temp=secl;
endcase
end

always@(Disp_Temp) 
begin
case(Disp_Temp)
4'b0000: Display=7'b0111111; //0
4'b0001: Display=7'b0000110; //1
4'b0010: Display=7'b1011011; //2
4'b0011: Display=7'b1001111; //3
4'b0100: Display=7'b1100110; //4
4'b0101: Display=7'b1101101; //5
4'b0110: Display=7'b1111101; //6
4'b0111: Display=7'b0000111; //7
4'b1000: Display=7'b1111111; //8
4'b1001: Display=7'b1101111; //9
4'b1010: Display=7'b1000000; //-
default: Display=7'b0000000; //全灭
endcase
end
endmodule