📄 songer.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity songer is
port(clk12mhz:in std_logic;
clk8hz:in std_logic;
code1:out std_logic_vector(3 downto 0);
high1:out std_logic;
spkout:out std_logic);
end;
architecture one of songer is
component notetabs
port(clk:in std_logic;
toneindex:out std_logic_vector(3 downto 0));
end component;
component tonetaba
port(index:in std_logic_vector(3 downto 0);
code :out std_logic_vector(3 downto 0);
high:out std_logic;
tone1:out std_logic_vector(10 downto 0));
end component;
component speakera
port(clk:in std_logic;
tone2:out std_logic_vector(10 downto 0);
spks:out std_logic);
end component;
signal tone:std_logic_vector(10 downto 0);
signal toneindex:std_logic_vector(3 downto 0);
begin
u1:notetabs port map(clk=>clk8hz,toneindex=>toneindex);
u2:tonetaba port map(index=>toneindex,tone1=>tone,code=>code1,high=>high1);
u3:speakera port map(clk=>clk12mhz,tone2=>tone,spks=>spkout);
end;
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