interlace.tan.rpt

来自「一个简单的交织实现程序」· RPT 代码 · 共 223 行 · 第 1/5 页

; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[1]                                                                           ; counter:inst8|series_addr[1]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.480 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[1]                                                                           ; counter:inst8|series_addr[4]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.480 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[1]                                                                           ; counter:inst8|series_addr[2]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.480 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[2]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg3  ; clk        ; clk      ; None                        ; None                      ; 1.375 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; counter:inst8|series_addr[0]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.469 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[3]                                                                           ; counter:inst8|series_addr[3]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.466 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[3]                                                                           ; counter:inst8|series_addr[1]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.466 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[3]                                                                           ; counter:inst8|series_addr[4]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.466 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[3]                                                                           ; counter:inst8|series_addr[2]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.466 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[5]                                                                                   ; RAM_MN_dual:inst5|Mux0~44                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.467 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[5]                                                                                   ; RAM_MN_dual2:inst6|dout                                                                                ; clk        ; clk      ; None                        ; None                      ; 1.463 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[1]                                                                                   ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~porta_we_reg        ; clk        ; clk      ; None                        ; None                      ; 1.378 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[3]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg3  ; clk        ; clk      ; None                        ; None                      ; 1.351 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[2]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg1 ; clk        ; clk      ; None                        ; None                      ; 1.347 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg4 ; clk        ; clk      ; None                        ; None                      ; 1.340 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[5]                                                                                   ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~porta_we_reg        ; clk        ; clk      ; None                        ; None                      ; 1.330 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; RAM_MN_dual:inst5|Mux0~53                                                                              ; RAM_MN_dual:inst5|dout                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.397 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; RAM_MN_dual:inst5|Mux0~53                                                                              ; RAM_MN_dual2:inst6|dout                                                                                ; clk        ; clk      ; None                        ; None                      ; 1.397 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[2]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg1  ; clk        ; clk      ; None                        ; None                      ; 1.297 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg2  ; clk        ; clk      ; None                        ; None                      ; 1.291 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg3 ; clk        ; clk      ; None                        ; None                      ; 1.287 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[4]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg4  ; clk        ; clk      ; None                        ; None                      ; 1.278 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0  ; clk        ; clk      ; None                        ; None                      ; 1.276 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[4]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg2  ; clk        ; clk      ; None                        ; None                      ; 1.251 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[2]                                                                                   ; RAM_MN_dual:inst5|dout                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.344 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[1]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg4  ; clk        ; clk      ; None                        ; None                      ; 1.229 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[1]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg3  ; clk        ; clk      ; None                        ; None                      ; 1.207 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[2]                                                                                   ; RAM_MN_dual:inst5|Mux0~44                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.314 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[4]                                                                           ; counter:inst8|series_addr[3]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.298 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[4]                                                                           ; counter:inst8|series_addr[1]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.298 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[4]                                                                           ; counter:inst8|series_addr[4]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.298 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[4]                                                                           ; counter:inst8|series_addr[2]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.298 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[2]                                                                                   ; RAM_MN_dual2:inst6|dout                                                                                ; clk        ; clk      ; None                        ; None                      ; 1.310 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; rom_mn_interlace:inst|interlace_addr[2]                                                                ; RAM_MN_dual:inst5|dout                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.285 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; rom_mn_interlace:inst|interlace_addr[2]                                                                ; RAM_MN_dual2:inst6|dout                                                                                ; clk        ; clk      ; None                        ; None                      ; 1.285 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[4]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg3  ; clk        ; clk      ; None                        ; None                      ; 1.186 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~porta_address_reg0 ; clk        ; clk      ; None                        ; None                      ; 1.170 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[2]                                                                                   ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~porta_we_reg        ; clk        ; clk      ; None                        ; None                      ; 1.177 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; counter:inst8|series_addr[3]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.212 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; counter:inst8|series_addr[1]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.212 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; counter:inst8|series_addr[4]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.212 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; counter:inst8|series_addr[2]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.212 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]