interlace.tan.rpt

来自「一个简单的交织实现程序」· RPT 代码 · 共 223 行 · 第 1/5 页

; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[4]                                                                                   ; RAM_MN_dual:inst5|dout                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.719 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[3]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg3 ; clk        ; clk      ; None                        ; None                      ; 1.604 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; counter:inst8|cnt[4]                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.668 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; counter:inst8|cnt[3]                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.668 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; counter:inst8|cnt[5]                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.668 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; counter:inst8|cnt[2]                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.668 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[4]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 1.577 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[4]                                                                                   ; RAM_MN_dual:inst5|Mux0~44                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.689 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[4]                                                                                   ; RAM_MN_dual2:inst6|dout                                                                                ; clk        ; clk      ; None                        ; None                      ; 1.685 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg1  ; clk        ; clk      ; None                        ; None                      ; 1.559 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[1]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg1 ; clk        ; clk      ; None                        ; None                      ; 1.555 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[3]                                                                                   ; RAM_MN_dual:inst5|dout                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.665 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[4]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg1 ; clk        ; clk      ; None                        ; None                      ; 1.535 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[4]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg4 ; clk        ; clk      ; None                        ; None                      ; 1.528 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[3]                                                                                   ; RAM_MN_dual:inst5|Mux0~44                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.635 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[4]                                                                                   ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~porta_we_reg        ; clk        ; clk      ; None                        ; None                      ; 1.552 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[3]                                                                                   ; RAM_MN_dual2:inst6|dout                                                                                ; clk        ; clk      ; None                        ; None                      ; 1.631 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~porta_datain_reg0   ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~porta_memory_reg0   ; clk        ; clk      ; None                        ; None                      ; 1.623 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~porta_datain_reg0  ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~porta_memory_reg0  ; clk        ; clk      ; None                        ; None                      ; 1.623 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[1]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg1  ; clk        ; clk      ; None                        ; None                      ; 1.505 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[0]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 ; clk        ; clk      ; None                        ; None                      ; 1.487 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[2]                                                                                   ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~porta_we_reg       ; clk        ; clk      ; None                        ; None                      ; 1.514 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[4]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg1  ; clk        ; clk      ; None                        ; None                      ; 1.485 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[5]                                                                                   ; counter:inst8|cnt[4]                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.582 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[5]                                                                                   ; counter:inst8|cnt[3]                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.582 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[5]                                                                                   ; counter:inst8|cnt[5]                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.582 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[5]                                                                                   ; counter:inst8|cnt[2]                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.582 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[1]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg4 ; clk        ; clk      ; None                        ; None                      ; 1.479 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[3]                                                                                   ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~porta_we_reg        ; clk        ; clk      ; None                        ; None                      ; 1.498 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[1]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg3 ; clk        ; clk      ; None                        ; None                      ; 1.460 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[4]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg3 ; clk        ; clk      ; None                        ; None                      ; 1.439 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[1]                                                                                   ; RAM_MN_dual:inst5|dout                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.545 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[1]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg2  ; clk        ; clk      ; None                        ; None                      ; 1.432 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[2]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg4  ; clk        ; clk      ; None                        ; None                      ; 1.432 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[3]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg2  ; clk        ; clk      ; None                        ; None                      ; 1.418 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[3]                                                                           ; RAM_MN_dual:inst5|altsyncram:ram_rtl_0|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg4  ; clk        ; clk      ; None                        ; None                      ; 1.408 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[1]                                                                                   ; RAM_MN_dual:inst5|Mux0~44                                                                              ; clk        ; clk      ; None                        ; None                      ; 1.515 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[1]                                                                                   ; counter:inst8|cnt[4]                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.497 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[1]                                                                                   ; counter:inst8|cnt[3]                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.497 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[1]                                                                                   ; counter:inst8|cnt[5]                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.497 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[1]                                                                                   ; counter:inst8|cnt[2]                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.497 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[1]                                                                                   ; RAM_MN_dual2:inst6|dout                                                                                ; clk        ; clk      ; None                        ; None                      ; 1.511 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[2]                                                                           ; RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 1.388 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|cnt[5]                                                                                   ; RAM_MN_dual:inst5|dout                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.497 ns                ;
; N/A                                     ; Restricted to 500.00 MHz ( period = 2.000 ns )      ; counter:inst8|series_addr[1]                                                                           ; counter:inst8|series_addr[3]                                                                           ; clk        ; clk      ; None                        ; None                      ; 1.480 ns                ;