jiaozhijiejiaozhi.map.rpt

一个简单的交织实现程序

+---------------------------------------------+---------+
; interlace:inst|rom_mn_seq:inst9|seq_addr[0] ; 14      ;
; Total number of inverted registers = 1      ;         ;
+---------------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------+
; 3:1                ; 5 bits    ; 10 ALUTs      ; 10 ALUTs             ; 0 ALUTs                ; Yes        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[4] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------+


+-------------------------------------------------------------+
; Source assignments for jieinterlace:inst1|RAM_MN_dual:inst5 ;
+----------------+-------+------+-----------------------------+
; Assignment     ; Value ; From ; To                          ;
+----------------+-------+------+-----------------------------+
; POWER_UP_LEVEL ; Low   ; -    ; flag~reg0                   ;
; POWER_UP_LEVEL ; Low   ; -    ; flag1                       ;
+----------------+-------+------+-----------------------------+


+----------------------------------------------------------+
; Source assignments for jieinterlace:inst1|counter2:inst1 ;
+----------------+-------+------+--------------------------+
; Assignment     ; Value ; From ; To                       ;
+----------------+-------+------+--------------------------+
; POWER_UP_LEVEL ; Low   ; -    ; cnt[1]                   ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[0]                   ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[2]                   ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[3]                   ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[4]                   ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[5]                   ;
; POWER_UP_LEVEL ; Low   ; -    ; series_addr1[0]          ;
; POWER_UP_LEVEL ; Low   ; -    ; series_addr1[1]          ;
; POWER_UP_LEVEL ; Low   ; -    ; series_addr1[2]          ;
; POWER_UP_LEVEL ; Low   ; -    ; series_addr1[3]          ;
; POWER_UP_LEVEL ; Low   ; -    ; series_addr1[4]          ;
+----------------+-------+------+--------------------------+


+---------------------------------------------------------+
; Source assignments for interlace:inst|RAM_MN_dual:inst2 ;
+----------------+-------+------+-------------------------+
; Assignment     ; Value ; From ; To                      ;
+----------------+-------+------+-------------------------+
; POWER_UP_LEVEL ; Low   ; -    ; flag~reg0               ;
; POWER_UP_LEVEL ; Low   ; -    ; flag1                   ;
+----------------+-------+------+-------------------------+


+----------------------------------------------------+
; Source assignments for interlace:inst|source:inst1 ;
+----------------+-------+------+--------------------+
; Assignment     ; Value ; From ; To                 ;
+----------------+-------+------+--------------------+
; POWER_UP_LEVEL ; Low   ; -    ; m[1]               ;
; POWER_UP_LEVEL ; Low   ; -    ; m[0]               ;
; POWER_UP_LEVEL ; Low   ; -    ; m[2]               ;
; POWER_UP_LEVEL ; Low   ; -    ; m[3]               ;
+----------------+-------+------+--------------------+


+------------------------------------------------------------------------------------------------------------------+
; Source assignments for jieinterlace:inst1|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_1qe1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                 ;
+---------------------------------+--------------------+------+----------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                  ;
+---------------------------------+--------------------+------+----------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Source assignments for jieinterlace:inst1|RAM_MN_dual:inst5|altsyncram:ram_rtl_1|altsyncram_1qe1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                ;
+---------------------------------+--------------------+------+---------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                 ;
+---------------------------------+--------------------+------+---------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Source assignments for interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                             ;
+---------------------------------+--------------------+------+------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                              ;
+---------------------------------+--------------------+------+------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Source assignments for interlace:inst|RAM_MN_dual:inst2|altsyncram:ram_rtl_3|altsyncram_1qe1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------+
; Assignment                      ; Value              ; From ; To                                            ;
+---------------------------------+--------------------+------+-----------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                             ;
+---------------------------------+--------------------+------+-----------------------------------------------+


+----------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: interlace:inst|counter1:inst5 ;
+----------------+-------+---------------------------------------------------+
; Parameter Name ; Value ; Type                                              ;
+----------------+-------+---------------------------------------------------+
; NN             ; 30    ; Untyped                                           ;
+----------------+-------+---------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: jieinterlace:inst1|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0 ;
+------------------------------------+-----------------+------------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                                 ;
+------------------------------------+-----------------+------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                              ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                         ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                       ;
; OPERATION_MODE                     ; DUAL_PORT       ; Untyped                                              ;
; WIDTH_A                            ; 1               ; Untyped                                              ;
; WIDTHAD_A                          ; 5               ; Untyped                                              ;
; NUMWORDS_A                         ; 32              ; Untyped                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                                              ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                              ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                              ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                              ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                              ;