jiaozhijiejiaozhi.map.rpt

来自「一个简单的交织实现程序」· RPT 代码 · 共 651 行 · 第 1/5 页

; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                          ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                          ;
; DEVICE_FAMILY                      ; Stratix II      ; Untyped                                          ;
; CBXI_PARAMETER                     ; altsyncram_1qe1 ; Untyped                                          ;
+------------------------------------+-----------------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: interlace:inst|RAM_MN_dual:inst2|altsyncram:ram_rtl_3 ;
+------------------------------------+-----------------+-------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                            ;
+------------------------------------+-----------------+-------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                         ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                      ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                    ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                    ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                  ;
; OPERATION_MODE                     ; DUAL_PORT       ; Untyped                                         ;
; WIDTH_A                            ; 1               ; Untyped                                         ;
; WIDTHAD_A                          ; 5               ; Untyped                                         ;
; NUMWORDS_A                         ; 32              ; Untyped                                         ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                                         ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                         ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                         ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                         ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                         ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                         ;
; WIDTH_B                            ; 1               ; Untyped                                         ;
; WIDTHAD_B                          ; 5               ; Untyped                                         ;
; NUMWORDS_B                         ; 32              ; Untyped                                         ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                         ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                         ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                         ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                         ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                         ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                         ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                         ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                         ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                         ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                         ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                         ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                         ;
; WIDTH_BYTEENA_A                    ; 1               ; Untyped                                         ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                         ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                         ;
; BYTE_SIZE                          ; 8               ; Untyped                                         ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                         ;
; INIT_FILE                          ; UNUSED          ; Untyped                                         ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                         ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                         ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                         ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                         ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                         ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                         ;
; DEVICE_FAMILY                      ; Stratix II      ; Untyped                                         ;
; CBXI_PARAMETER                     ; altsyncram_1qe1 ; Untyped                                         ;
+------------------------------------+-----------------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Apr 09 12:10:31 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jiaozhijiejiaozhi -c jiaozhijiejiaozhi
Info: Found 1 design units, including 1 entities, in source file jiaozhijiejiaozhi.bdf
    Info: Found entity 1: jiaozhijiejiaozhi
Info: Found 2 design units, including 1 entities, in source file RAM_MN_dual.vhd
    Info: Found design unit 1: RAM_MN_dual-beha
    Info: Found entity 1: RAM_MN_dual
Info: Found 1 design units, including 1 entities, in source file interlace.bdf
    Info: Found entity 1: interlace
Info: Found 1 design units, including 1 entities, in source file cobination.v
    Info: Found entity 1: cobination
Info: Found 1 design units, including 1 entities, in source file jieinterlace.bdf
    Info: Found entity 1: jieinterlace
Info: Found 1 design units, including 1 entities, in source file counter.v
    Info: Found entity 1: counter
Warning: Can't analyze file -- file F:/liangshuo程序/1/fen_zu_interlacing/counter1.vhd is missing
Info: Found 1 design units, including 1 entities, in source file counter1.v
    Info: Found entity 1: counter1
Info: Found 2 design units, including 1 entities, in source file counter2.vhd
    Info: Found design unit 1: counter2-a
    Info: Found entity 1: counter2
Info: Found 2 design units, including 1 entities, in source file rom_mn_interlace.vhd
    Info: Found design unit 1: rom_mn_interlace-beha
    Info: Found entity 1: rom_mn_interlace
Info: Elaborating entity "jiaozhijiejiaozhi" for the top level hierarchy
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Block or symbol "jieinterlace" of instance "inst1" overlaps another block or symbol
Info: Elaborating entity "jieinterlace" for hierarchy "jieinterlace:inst1"
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Info: Elaborating entity "RAM_MN_dual" for hierarchy "jieinterlace:inst1|RAM_MN_dual:inst5"
Info: Elaborating entity "counter2" for hierarchy "jieinterlace:inst1|counter2:inst1"
Info: Elaborating entity "rom_mn_interlace" for hierarchy "jieinterlace:inst1|rom_mn_interlace:inst"
Warning: Using design file rom_mn_seq.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: rom_mn_seq-beha
    Info: Found entity 1: rom_mn_seq
Info: Elaborating entity "rom_mn_seq" for hierarchy "jieinterlace:inst1|rom_mn_seq:inst2"
Warning: Using design file RAM_MN_dual2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: RAM_MN_dual2-beha
    Info: Found entity 1: RAM_MN_dual2
Info: Elaborating entity "RAM_MN_dual2" for hierarchy "jieinterlace:inst1|RAM_MN_dual2:inst6"
Info: Elaborating entity "cobination" for hierarchy "jieinterlace:inst1|cobination:inst12"
Info: Elaborating entity "interlace" for hierarchy "interlace:inst"
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Info: Elaborating entity "counter1" for hierarchy "interlace:inst|counter1:inst5"
Warning: Using design file source.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: source-a
    Info: Found entity 1: source
Info: Elaborating entity "source" for hierarchy "interlace:inst|source:inst1"
Warning: Created node "jieinterlace:inst1|RAM_MN_dual2:inst6|ram[0]~60" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design.
Warning: Created node "jieinterlace:inst1|RAM_MN_dual:inst5|ram[0]~60" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Func