📄 jiaozhijiejiaozhi.map.rpt
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; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
+------------------------------------------------------------+--------------------+--------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------+
; jiaozhijiejiaozhi.bdf ; yes ; User Block Diagram/Schematic File ; F:/liangshuo程序/1/fen_zu_interlacing/jiaozhijiejiaozhi.bdf ;
; RAM_MN_dual.vhd ; yes ; User VHDL File ; F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd ;
; interlace.bdf ; yes ; User Block Diagram/Schematic File ; F:/liangshuo程序/1/fen_zu_interlacing/interlace.bdf ;
; cobination.v ; yes ; User Verilog HDL File ; F:/liangshuo程序/1/fen_zu_interlacing/cobination.v ;
; jieinterlace.bdf ; yes ; User Block Diagram/Schematic File ; F:/liangshuo程序/1/fen_zu_interlacing/jieinterlace.bdf ;
; counter1.v ; yes ; User Verilog HDL File ; F:/liangshuo程序/1/fen_zu_interlacing/counter1.v ;
; counter2.vhd ; yes ; User VHDL File ; F:/liangshuo程序/1/fen_zu_interlacing/counter2.vhd ;
; rom_mn_interlace.vhd ; yes ; User VHDL File ; F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_interlace.vhd ;
; rom_mn_seq.vhd ; yes ; Other ; F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_seq.vhd ;
; RAM_MN_dual2.vhd ; yes ; Other ; F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd ;
; source.vhd ; yes ; Other ; F:/liangshuo程序/1/fen_zu_interlacing/source.vhd ;
; altsyncram.tdf ; yes ; Megafunction ; d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Other ; d:/program files/altera/quartus60/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc ; yes ; Other ; d:/program files/altera/quartus60/libraries/megafunctions/lpm_mux.inc ;
; lpm_decode.inc ; yes ; Other ; d:/program files/altera/quartus60/libraries/megafunctions/lpm_decode.inc ;
; aglobal60.inc ; yes ; Other ; d:/program files/altera/quartus60/libraries/megafunctions/aglobal60.inc ;
; altsyncram.inc ; yes ; Other ; d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.inc ;
; a_rdenreg.inc ; yes ; Other ; d:/program files/altera/quartus60/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Other ; d:/program files/altera/quartus60/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Other ; d:/program files/altera/quartus60/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Other ; d:/program files/altera/quartus60/libraries/megafunctions/altdpram.inc ;
; altqpram.inc ; yes ; Other ; d:/program files/altera/quartus60/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_1qe1.tdf ; yes ; Auto-Generated Megafunction ; F:/liangshuo程序/1/fen_zu_interlacing/db/altsyncram_1qe1.tdf ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------+
+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------------------+-------+
; Resource ; Usage ;
+-----------------------------------------------+-------+
; Estimated Total ALUTs ; 48 ;
; Total combinational functions ; 39 ;
; ALUT usage by number of inputs ; ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 2 ;
; -- 5 input functions ; 12 ;
; -- 4 input functions ; 2 ;
; -- <=3 input functions ; 23 ;
; -- Combinational cells for routing ; 0 ;
; ALUTs by mode ; ;
; -- normal mode ; 25 ;
; -- extended LUT mode ; 0 ;
; -- arithmetic mode ; 14 ;
; -- shared arithmetic mode ; 0 ;
; Total registers ; 35 ;
; Estimated ALMs: partially or completely used ; 24 ;
; I/O pins ; 16 ;
; Total memory bits ; 128 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 38 ;
; Total fan-out ; 273 ;
; Average fan-out ; 2.90 ;
+-----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------------+-------------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------------------------+-------------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------+
; |jiaozhijiejiaozhi ; 39 (0) ; 35 (0) ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 ; 0 ; |jiaozhijiejiaozhi ;
; |interlace:inst| ; 18 (0) ; 18 (2) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|interlace:inst ;
; |RAM_MN_dual2:inst6| ; 1 (1) ; 1 (1) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual2:inst6 ;
; |altsyncram:ram_rtl_2| ; 0 (0) ; 0 (0) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2 ;
; |altsyncram_1qe1:auto_generated| ; 0 (0) ; 0 (0) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated ;
; |RAM_MN_dual:inst2| ; 1 (1) ; 3 (3) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2 ;
; |altsyncram:ram_rtl_3| ; 0 (0) ; 0 (0) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2|altsyncram:ram_rtl_3 ;
; |altsyncram_1qe1:auto_generated| ; 0 (0) ; 0 (0) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2|altsyncram:ram_rtl_3|altsyncram_1qe1:auto_generated ;
; |cobination:inst3| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|interlace:inst|cobination:inst3 ;
; |counter1:inst5| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|interlace:inst|counter1:inst5 ;
; |rom_mn_interlace:inst| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|interlace:inst|rom_mn_interlace:inst ;
; |rom_mn_seq:inst9| ; 2 (2) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|interlace:inst|rom_mn_seq:inst9 ;
; |source:inst1| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|interlace:inst|source:inst1 ;
; |jieinterlace:inst1| ; 21 (0) ; 17 (0) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|jieinterlace:inst1 ;
; |RAM_MN_dual2:inst6| ; 1 (1) ; 1 (1) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual2:inst6 ;
; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 (0) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0 ;
; |altsyncram_1qe1:auto_generated| ; 0 (0) ; 0 (0) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_1qe1:auto_generated ;
; |RAM_MN_dual:inst5| ; 1 (1) ; 1 (1) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual:inst5 ;
; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 (0) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual:inst5|altsyncram:ram_rtl_1 ;
; |altsyncram_1qe1:auto_generated| ; 0 (0) ; 0 (0) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual:inst5|altsyncram:ram_rtl_1|altsyncram_1qe1:auto_generated ;
; |cobination:inst12| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|jieinterlace:inst1|cobination:inst12 ;
; |counter2:inst1| ; 13 (13) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1 ;
; |rom_mn_interlace:inst| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_interlace:inst ;
; |rom_mn_seq:inst2| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_seq:inst2 ;
+----------------------------------------------+-------------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 1 ; 32 ; 1 ; 32 ; None ;
; interlace:inst|RAM_MN_dual:inst2|altsyncram:ram_rtl_3|altsyncram_1qe1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 1 ; 32 ; 1 ; 32 ; None ;
; jieinterlace:inst1|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_1qe1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 1 ; 32 ; 1 ; 32 ; None ;
; jieinterlace:inst1|RAM_MN_dual:inst5|altsyncram:ram_rtl_1|altsyncram_1qe1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 1 ; 32 ; 1 ; 32 ; None ;
+------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 35 ;
; Number of registers using Synchronous Clear ; 13 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------+
; Inverted Register Statistics ;
+---------------------------------------------+---------+
; Inverted Register ; Fan out ;
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