📄 usbin_v1.7.v
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/*
程序说明:
用于cy7c68013与fpga的从FIFO通讯.版本1.5.完成于2007.10.31
*/
/*
硬件定义:
EP2为收端点,EP6为发端点,4*512缓冲;FLAGA为EP2空标志,FLAGB为EP6满标志,低电平有效;
*/
/*
使用说明:
avalon总线读写.缓存为32位128个字.
读操作为读接收缓存,写操作为写发送缓存,例:
temp=IORD(usbbase,i);
IOWR(usbbase,i,temp);
i为0~127.
读第129字为读IP核状态,低三位有效,分别为usb_busy,wrram_full,rdram_full,
usb_busy为高表示忙,wrram_full为高表示接收缓存有未处理新数据,rdram_full为高表示发送缓存有未发送新数据.例:
temp=IORD(usbbase,128);
写第129字为写IP核命令,低两位有效,分别为send,get,send写1为发送发送缓存数据.get写1为准备好接收数据.例:
IOWR(usbbase,128,1);
IOWR(usbbase,128,2);
*/
module usbin (U_IFCLK,U_FLAGA,U_FLAGB,U_ADR,U_SLWR,U_SLRD,U_SLOE,UD,//,U_SLCS
clk,address,readdata,writedata,read,write,
led0,led1);//,rdram_usb_wr,key0,key1,
input U_IFCLK,U_FLAGA,U_FLAGB;//低有效
output U_SLWR,U_SLRD,U_SLOE;//U_PKTEND,//低有效,U_SLCS
output[1:0] U_ADR;
inout[15:0] UD;
reg[15:0] UD;
reg U_SLWR=1,U_SLRD=1,U_SLOE=1;//U_PKTEND,U_SLCS,
reg[1:0] U_ADR;
//output rdram_usb_wr;
//-------------------实验接口-----------------------------------
//input key0,key1;
output led0,led1;
//-------------------程序变量-----------------------------------
reg[3:0] usb_state;
reg[8:0] datacount;
reg rdram_full=0,wrram_full=0,usb_busy;
reg rdram_full_clr=0,wrram_full_set=0;
//reg read_state;
//-------------------模块接线-----------------------------------
//reg wrram_usb_oe;
reg rdram_usb_wr;
wire[15:0] wrram_out;
wire[31:0] rdram_out;
//-------------------AVALON接口-----------------------------------
input clk,write,read;
input[31:0] writedata;
input[7:0] address;
output[31:0] readdata;
//reg[31:0] readdata;
/////////////////////////////////////////////////////////////
rdram RDRAM (UD,address[6:0],clk,read,datacount[7:0],U_IFCLK,rdram_usb_wr,rdram_out);
wrram WRRAM (writedata,datacount[7:0],U_IFCLK,address[6:0],clk,(write&(~address[7])),wrram_out);
/////////////////////////////////////////////////////////////
always@(posedge U_IFCLK) begin
if(rdram_full_clr==1) rdram_full<=0;
if(wrram_full_set==1) wrram_full<=1;
case(usb_state)
0 : begin//准备
U_SLWR<=1;
U_SLOE<=1;
U_SLRD<=1;
UD<=16'HZZZZ;
rdram_usb_wr<=0;
if(rdram_full==0 && U_FLAGA==1)begin//接收ram空,FIFO非空--接收
datacount<=0;
U_ADR<=0;//EP2
usb_state<=1;
usb_busy<=1;
end
else if(wrram_full==1 && U_FLAGB==1)begin//发送ram满,FIFO非满--发送
datacount<=0;
U_ADR<=2;//EP6
usb_state<=7;
usb_busy<=1;
end
end
1 : begin
U_SLRD<=0;
U_SLOE<=0;
rdram_usb_wr<=1;
usb_state<=2;
end
2 : begin//数据输入
datacount<=datacount+1;
if(datacount>=254)begin
usb_state<=3;
end
end
3 : begin
U_SLOE<=1;
U_SLRD<=1;
rdram_usb_wr<=0;
rdram_full<=1;
usb_busy<=0;
usb_state<=0;
end
7 : begin //发送
datacount<=datacount+1;
UD<=wrram_out;
if(datacount>=2) U_SLWR<=0;
if(datacount>=257) begin//发送完成
usb_state<=8;
end
end
8 : begin//发送完成
U_SLWR<=1;
UD<=16'HZZZZ;
wrram_full<=0;
usb_state<=0;
usb_busy<=0;
end
default:begin
usb_state<=0;
U_SLWR<=1;
U_SLOE<=1;
U_SLRD<=1;
UD<=16'HZZZZ;
rdram_usb_wr<=0;
end
endcase
end
////////////////////////////////////////////////////////////////////////////////写操作
reg[1:0] avalon_write_state;
always@(posedge clk) begin
case(avalon_write_state)
0 : begin
if(address==8'b10000000 && write==1) begin
if(writedata[0]==1) begin
rdram_full_clr<=1;
avalon_write_state<=1;
end
if(writedata[1]==1) begin
wrram_full_set<=1;
avalon_write_state<=1;
end
end
end
1 : begin//延时确保usb模块采集到高电平
avalon_write_state<=2;
end
2 : begin
avalon_write_state<=3;
end
3 : begin
avalon_write_state<=0;
rdram_full_clr<=0;
wrram_full_set<=0;
end
default : begin
rdram_full_clr<=0;
wrram_full_set<=0;
avalon_write_state<=0;
end
endcase
end
//---------------------------------------------------读操作
/*
always@(posedge clk) begin
if(address==8'b10000000) begin
readdata<={29'h00000000,usb_busy,wrram_full,rdram_full};
end
else begin
readdata<=rdram_out;
end
end*/
assign readdata = address==8'b10000000 ? {29'h00000000,usb_busy,wrram_full,rdram_full} : rdram_out ;
//assign readdata = rdram_out;
////////////////////////////////////////////////////////////////////////////////
assign led1=wrram_full;
assign led0=rdram_full;
//rdram RDRAM (UD,address,clock,0,datacount[7:0],U_IFCLK,rdram_usb_wr,readdata);
//wrram WRRAM (writedata,datacount[7:0],U_IFCLK,address,clock,0,wrram_out_temp);
endmodule
/////////////////////////////////////////////////////////////////////////////////
module wrram (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [31:0] data;
input [7:0] rdaddress;
input rdclock;
input [6:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({16{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.init_file = "cy7c68013.mif",
altsyncram_component.init_file_layout = "PORT_B",
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 128,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 7,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
endmodule
//////////////////////////////////////////////////////////////////////
module rdram (
data,
rdaddress,
rdclock,
rden,
wraddress,
wrclock,
wren,
q);
input [15:0] data;
input [6:0] rdaddress;
input rdclock;
input rden;
input [7:0] wraddress;
input wrclock;
input wren;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.rden_b (rden),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.init_file = "cy7c68013.mif",
altsyncram_component.init_file_layout = "PORT_B",
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 128,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_aclr_b = "NONE",
altsyncram_component.rdcontrol_reg_b = "CLOCK1",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 7,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
endmodule
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