i2c_eeprom.fit.qmsg

使用VHDL编写的操作EEPROM来控制iic的读写操作

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "i2c_top:inst\|clk_div  " "Info: Automatically promoted node i2c_top:inst\|clk_div " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|clk_div~43 " "Info: Destination node i2c_top:inst\|clk_div~43" {  } { { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|clk_div~43 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|clk_div } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pld_CLEAR_n (placed in PIN 24 (CLK1, LVDSCLK0n, Input)) " "Info: Automatically promoted node pld_CLEAR_n (placed in PIN 24 (CLK1, LVDSCLK0n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|data_r\[0\]~716 " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|data_r\[0\]~716" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 268 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0]~716 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_buf\[1\] " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_buf\[1\]" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 268 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|stop_buf[1] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8in_state.sh8in_bit6~129 " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8in_state.sh8in_bit6~129" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 31 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit6~129 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|head_state.head_bit " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|head_state.head_bit" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 32 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|head_state.head_bit } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_end " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_end" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 33 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_end } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8in_state.sh8in_bit7~67 " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8in_state.sh8in_bit7~67" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 31 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit7~67 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_bit " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_bit" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 33 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_buf\[0\] " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_buf\[0\]" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 268 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|stop_buf[0] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_buf\[7\]~567 " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_buf\[7\]~567" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 268 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[7]~567 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_state.sh8out_bit6 " "Info: Destination node i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_state.sh8out_bit6" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 30 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit6 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/80/quartus/bin/pin_planner.ppl" { pld_CLEAR_n } } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "pld_CLEAR_n" } } } } { "I2c_eeprom.bdf" "" { Schematic "D:/Altera/release/Demo/logic/EEPROM/I2c_eeprom.bdf" { { 224 -48 120 240 "pld_CLEAR_n" "" } } } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { pld_CLEAR_n } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 0}