i2c_eeprom.hier_info

使用VHDL编写的操作EEPROM来控制iic的读写操作

|I2c_eeprom
HC_SI <= hc164_driver:inst1.hc_si
clk1 => hc164_driver:inst1.clk
clk1 => i2c_top:inst.clk
pld_CLEAR_n => hc164_driver:inst1.rst_n
pld_CLEAR_n => i2c_top:inst.rst_n
I2C_sda <= i2c_top:inst.sda
HC_CP <= hc164_driver:inst1.hc_cp
I2C_clk <= i2c_top:inst.scl


|I2c_eeprom|hc164_driver:inst1
clk => clk_cnt[15].CLK
clk => clk_cnt[14].CLK
clk => clk_cnt[13].CLK
clk => clk_cnt[12].CLK
clk => clk_cnt[11].CLK
clk => clk_cnt[10].CLK
clk => clk_cnt[9].CLK
clk => clk_cnt[8].CLK
clk => clk_cnt[7].CLK
clk => clk_cnt[6].CLK
clk => clk_cnt[5].CLK
clk => clk_cnt[4].CLK
clk => clk_cnt[3].CLK
clk => clk_cnt[2].CLK
clk => clk_cnt[1].CLK
clk => clk_cnt[0].CLK
clk => seg_led_num[1].CLK
clk => seg_led_num[0].CLK
clk => tx_cnt[5].CLK
clk => tx_cnt[4].CLK
clk => tx_cnt[3].CLK
clk => tx_cnt[2].CLK
clk => tx_cnt[1].CLK
clk => tx_cnt[0].CLK
clk => hc_cp~reg0.CLK
rst_n => tx_cnt[0].ACLR
rst_n => tx_cnt[1].ACLR
rst_n => tx_cnt[2].ACLR
rst_n => tx_cnt[3].ACLR
rst_n => tx_cnt[4].ACLR
rst_n => tx_cnt[5].ACLR
rst_n => seg_led_num[0].ACLR
rst_n => seg_led_num[1].ACLR
rst_n => hc_cp~reg0.ACLR
rst_n => clk_cnt[15].ACLR
rst_n => clk_cnt[14].ACLR
rst_n => clk_cnt[13].ACLR
rst_n => clk_cnt[12].ACLR
rst_n => clk_cnt[11].ACLR
rst_n => clk_cnt[10].ACLR
rst_n => clk_cnt[9].ACLR
rst_n => clk_cnt[8].ACLR
rst_n => clk_cnt[7].ACLR
rst_n => clk_cnt[6].ACLR
rst_n => clk_cnt[5].ACLR
rst_n => clk_cnt[4].ACLR
rst_n => clk_cnt[3].ACLR
rst_n => clk_cnt[2].ACLR
rst_n => clk_cnt[1].ACLR
rst_n => clk_cnt[0].ACLR
led[0] => Mux5.IN16
led[1] => Mux5.IN17
led[2] => Mux5.IN18
led[3] => Mux5.IN19
dot[0] => Mux4.IN3
dot[1] => Mux4.IN2
dot[2] => Mux4.IN1
dot[3] => Mux4.IN0
seg_value[0] => Mux3.IN3
seg_value[1] => Mux2.IN3
seg_value[2] => Mux1.IN3
seg_value[3] => Mux0.IN3
seg_value[4] => Mux3.IN2
seg_value[5] => Mux2.IN2
seg_value[6] => Mux1.IN2
seg_value[7] => Mux0.IN2
seg_value[8] => Mux3.IN1
seg_value[9] => Mux2.IN1
seg_value[10] => Mux1.IN1
seg_value[11] => Mux0.IN1
seg_value[12] => Mux3.IN0
seg_value[13] => Mux2.IN0
seg_value[14] => Mux1.IN0
seg_value[15] => Mux0.IN0
hc_cp <= hc_cp~reg0.DB_MAX_OUTPUT_PORT_TYPE
hc_si <= Mux5.DB_MAX_OUTPUT_PORT_TYPE


|I2c_eeprom|i2c_top:inst
clk => clk_cnt[11].CLK
clk => clk_cnt[10].CLK
clk => clk_cnt[9].CLK
clk => clk_cnt[8].CLK
clk => clk_cnt[7].CLK
clk => clk_cnt[6].CLK
clk => clk_cnt[5].CLK
clk => clk_cnt[4].CLK
clk => clk_cnt[3].CLK
clk => clk_cnt[2].CLK
clk => clk_cnt[1].CLK
clk => clk_cnt[0].CLK
clk => clk_div.CLK
rst_n => rst_n~0.IN1
sda <= i2c_wr:i2c_wr_inst.sda
scl <= i2c_wr:i2c_wr_inst.scl
data_rep[0] <= data_rep[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[1] <= data_rep[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[2] <= data_rep[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[3] <= data_rep[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[4] <= data_rep[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[5] <= data_rep[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[6] <= data_rep[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[7] <= data_rep[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[8] <= data_rep[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[9] <= data_rep[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[10] <= data_rep[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[11] <= data_rep[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[12] <= data_rep[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[13] <= data_rep[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[14] <= data_rep[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_rep[15] <= data_rep[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|I2c_eeprom|i2c_top:inst|i2c_wr:i2c_wr_inst
clk => link_write.CLK
clk => link_head.CLK
clk => link_stop.CLK
clk => link_sda.CLK
clk => ack~reg0.CLK
clk => rf.CLK
clk => wf.CLK
clk => ff.CLK
clk => head_buf[1].CLK
clk => head_buf[0].CLK
clk => stop_buf[1].CLK
clk => stop_buf[0].CLK
clk => sh8out_buf[7].CLK
clk => sh8out_buf[6].CLK
clk => sh8out_buf[5].CLK
clk => sh8out_buf[4].CLK
clk => sh8out_buf[3].CLK
clk => sh8out_buf[2].CLK
clk => sh8out_buf[1].CLK
clk => sh8out_buf[0].CLK
clk => data_r[7]~reg0.CLK
clk => data_r[6]~reg0.CLK
clk => data_r[5]~reg0.CLK
clk => data_r[4]~reg0.CLK
clk => data_r[3]~reg0.CLK
clk => data_r[2]~reg0.CLK
clk => data_r[1]~reg0.CLK
clk => data_r[0]~reg0.CLK
clk => scl~reg0.CLK
clk => sh8in_state~20.IN1
clk => stop_state~11.IN1
clk => sh8out_state~54.IN1
clk => head_state~12.IN1
clk => main_state~52.IN1
rst_n => scl~reg0.ACLR
rst_n => link_write.ACLR
rst_n => link_head.ACLR
rst_n => link_stop.ACLR
rst_n => link_sda.ACLR
rst_n => ack~reg0.ACLR
rst_n => rf.ACLR
rst_n => wf.ACLR
rst_n => ff.ACLR
rst_n => head_buf[1].ACLR
rst_n => head_buf[0].ACLR
rst_n => head_state.head_begin~0.OUTPUTSELECT
rst_n => head_state.head_bit~0.OUTPUTSELECT
rst_n => head_state.head_end~0.OUTPUTSELECT
rst_n => sh8out_state.sh8out_bit7~0.OUTPUTSELECT
rst_n => sh8out_state.sh8out_bit6~0.OUTPUTSELECT
rst_n => sh8out_state.sh8out_bit5~0.OUTPUTSELECT
rst_n => sh8out_state.sh8out_bit4~0.OUTPUTSELECT
rst_n => sh8out_state.sh8out_bit3~0.OUTPUTSELECT
rst_n => sh8out_state.sh8out_bit2~0.OUTPUTSELECT
rst_n => sh8out_state.sh8out_bit1~0.OUTPUTSELECT
rst_n => sh8out_state.sh8out_bit0~0.OUTPUTSELECT
rst_n => sh8out_state.sh8out_end~0.OUTPUTSELECT
rst_n => stop_state.stop_begin~0.OUTPUTSELECT
rst_n => stop_state.stop_bit~0.OUTPUTSELECT
rst_n => stop_state.stop_end~0.OUTPUTSELECT
rst_n => sh8in_state.sh8in_begin~0.OUTPUTSELECT
rst_n => sh8in_state.sh8in_bit7~0.OUTPUTSELECT
rst_n => sh8in_state.sh8in_bit6~0.OUTPUTSELECT
rst_n => sh8in_state.sh8in_bit5~0.OUTPUTSELECT
rst_n => sh8in_state.sh8in_bit4~0.OUTPUTSELECT
rst_n => sh8in_state.sh8in_bit3~0.OUTPUTSELECT
rst_n => sh8in_state.sh8in_bit2~0.OUTPUTSELECT
rst_n => sh8in_state.sh8in_bit1~0.OUTPUTSELECT
rst_n => sh8in_state.sh8in_bit0~0.OUTPUTSELECT
rst_n => sh8in_state.sh8in_end~0.OUTPUTSELECT
rst_n => data_r[0]~reg0.ENA
rst_n => stop_buf[1].ENA
rst_n => stop_buf[0].ENA
rst_n => sh8out_buf[7].ENA
rst_n => sh8out_buf[6].ENA
rst_n => sh8out_buf[5].ENA
rst_n => sh8out_buf[4].ENA
rst_n => sh8out_buf[3].ENA
rst_n => sh8out_buf[2].ENA
rst_n => sh8out_buf[1].ENA
rst_n => sh8out_buf[0].ENA
rst_n => data_r[7]~reg0.ENA
rst_n => data_r[6]~reg0.ENA
rst_n => data_r[5]~reg0.ENA
rst_n => data_r[4]~reg0.ENA
rst_n => data_r[3]~reg0.ENA
rst_n => data_r[2]~reg0.ENA
rst_n => data_r[1]~reg0.ENA
rst_n => main_state~53.IN1
wr => rf~0.OUTPUTSELECT
wr => main_state~1.OUTPUTSELECT
wr => main_state~0.OUTPUTSELECT
wr => wf~1.OUTPUTSELECT
rd => main_state~1.DATAA
rd => rf~0.DATAA
rd => wf~0.OUTPUTSELECT
rd => main_state~0.DATAA
addr[0] => sh8out_buf~24.DATAA
addr[1] => sh8out_buf~23.DATAA
addr[2] => sh8out_buf~22.DATAA
addr[3] => sh8out_buf~21.DATAA
addr[4] => sh8out_buf~20.DATAA
addr[5] => sh8out_buf~19.DATAA
addr[6] => sh8out_buf~18.DATAA
addr[7] => sh8out_buf~17.DATAA
addr[8] => sh8out_buf~6.DATAA
addr[9] => sh8out_buf~5.DATAA
addr[10] => sh8out_buf~4.DATAA
data_w[0] => sh8out_buf~32.DATAB
data_w[1] => sh8out_buf~31.DATAB
data_w[2] => sh8out_buf~30.DATAB
data_w[3] => sh8out_buf~29.DATAB
data_w[4] => sh8out_buf~28.DATAB
data_w[5] => sh8out_buf~27.DATAB
data_w[6] => sh8out_buf~26.DATAB
data_w[7] => sh8out_buf~25.DATAB
data_r[0] <= data_r[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_r[1] <= data_r[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_r[2] <= data_r[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_r[3] <= data_r[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_r[4] <= data_r[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_r[5] <= data_r[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_r[6] <= data_r[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_r[7] <= data_r[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ack <= ack~reg0.DB_MAX_OUTPUT_PORT_TYPE
scl <= scl~reg0.DB_MAX_OUTPUT_PORT_TYPE
sda <= sda~0