i2c_eeprom.tan.qmsg

使用VHDL编写的操作EEPROM来控制iic的读写操作

{ "Info" "ITDB_TSU_RESULT" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|data_r\[0\] I2C_sda clk1 1.778 ns register " "Info: tsu for register \"i2c_top:inst\|i2c_wr:i2c_wr_inst\|data_r\[0\]\" (data pin = \"I2C_sda\", clock pin = \"clk1\") is 1.778 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.786 ns + Longest pin register " "Info: + Longest pin to register delay is 8.786 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2C_sda 1 PIN PIN_185 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_185; Fanout = 1; PIN Node = 'I2C_sda'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_sda } "NODE_NAME" } } { "I2c_eeprom.bdf" "" { Schematic "D:/Altera/release/Demo/logic/EEPROM/I2c_eeprom.bdf" { { 208 552 728 224 "I2C_sda" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.954 ns) 0.954 ns I2C_sda~0 2 COMB IOC_X14_Y19_N1 8 " "Info: 2: + IC(0.000 ns) + CELL(0.954 ns) = 0.954 ns; Loc. = IOC_X14_Y19_N1; Fanout = 8; COMB Node = 'I2C_sda~0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.954 ns" { I2C_sda I2C_sda~0 } "NODE_NAME" } } { "I2c_eeprom.bdf" "" { Schematic "D:/Altera/release/Demo/logic/EEPROM/I2c_eeprom.bdf" { { 208 552 728 224 "I2C_sda" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.073 ns) + CELL(0.651 ns) 8.678 ns i2c_top:inst\|i2c_wr:i2c_wr_inst\|data_r\[0\]~718 3 COMB LCCOMB_X31_Y8_N18 1 " "Info: 3: + IC(7.073 ns) + CELL(0.651 ns) = 8.678 ns; Loc. = LCCOMB_X31_Y8_N18; Fanout = 1; COMB Node = 'i2c_top:inst\|i2c_wr:i2c_wr_inst\|data_r\[0\]~718'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.724 ns" { I2C_sda~0 i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0]~718 } "NODE_NAME" } } { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 268 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.786 ns i2c_top:inst\|i2c_wr:i2c_wr_inst\|data_r\[0\] 4 REG LCFF_X31_Y8_N19 2 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.786 ns; Loc. = LCFF_X31_Y8_N19; Fanout = 2; REG Node = 'i2c_top:inst\|i2c_wr:i2c_wr_inst\|data_r\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0]~718 i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0] } "NODE_NAME" } } { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 268 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.713 ns ( 19.50 % ) " "Info: Total cell delay = 1.713 ns ( 19.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.073 ns ( 80.50 % ) " "Info: Total interconnect delay = 7.073 ns ( 80.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.786 ns" { I2C_sda I2C_sda~0 i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0]~718 i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.786 ns" { I2C_sda {} I2C_sda~0 {} i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0]~718 {} i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0] {} } { 0.000ns 0.000ns 7.073ns 0.000ns } { 0.000ns 0.954ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 268 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 6.968 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to destination register is 6.968 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk1 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "I2c_eeprom.bdf" "" { Schematic "D:/Altera/release/Demo/logic/EEPROM/I2c_eeprom.bdf" { { 208 -48 120 224 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.105 ns) + CELL(0.970 ns) 4.215 ns i2c_top:inst\|clk_div 2 REG LCFF_X33_Y7_N1 2 " "Info: 2: + IC(2.105 ns) + CELL(0.970 ns) = 4.215 ns; Loc. = LCFF_X33_Y7_N1; Fanout = 2; REG Node = 'i2c_top:inst\|clk_div'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.075 ns" { clk1 i2c_top:inst|clk_div } "NODE_NAME" } } { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.000 ns) 5.402 ns i2c_top:inst\|clk_div~clkctrl 3 COMB CLKCTRL_G4 115 " "Info: 3: + IC(1.187 ns) + CELL(0.000 ns) = 5.402 ns; Loc. = CLKCTRL_G4; Fanout = 115; COMB Node = 'i2c_top:inst\|clk_div~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl } "NODE_NAME" } } { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.666 ns) 6.968 ns i2c_top:inst\|i2c_wr:i2c_wr_inst\|data_r\[0\] 4 REG LCFF_X31_Y8_N19 2 " "Info: 4: + IC(0.900 ns) + CELL(0.666 ns) = 6.968 ns; Loc. = LCFF_X31_Y8_N19; Fanout = 2; REG Node = 'i2c_top:inst\|i2c_wr:i2c_wr_inst\|data_r\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.566 ns" { i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0] } "NODE_NAME" } } { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 268 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 39.84 % ) " "Info: Total cell delay = 2.776 ns ( 39.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.192 ns ( 60.16 % ) " "Info: Total interconnect delay = 4.192 ns ( 60.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.968 ns" { clk1 i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.968 ns" { clk1 {} clk1~combout {} i2c_top:inst|clk_div {} i2c_top:inst|clk_div~clkctrl {} i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0] {} } { 0.000ns 0.000ns 2.105ns 1.187ns 0.900ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.786 ns" { I2C_sda I2C_sda~0 i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0]~718 i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.786 ns" { I2C_sda {} I2C_sda~0 {} i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0]~718 {} i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0] {} } { 0.000ns 0.000ns 7.073ns 0.000ns } { 0.000ns 0.954ns 0.651ns 0.108ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.968 ns" { clk1 i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.968 ns" { clk1 {} clk1~combout {} i2c_top:inst|clk_div {} i2c_top:inst|clk_div~clkctrl {} i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0] {} } { 0.000ns 0.000ns 2.105ns 1.187ns 0.900ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 HC_SI i2c_top:inst\|data_rep\[10\] 20.743 ns register " "Info: tco from clock \"clk1\" to destination pin \"HC_SI\" through register \"i2c_top:inst\|data_rep\[10\]\" is 20.743 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 6.947 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to source register is 6.947 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk1 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "I2c_eeprom.bdf" "" { Schematic "D:/Altera/release/Demo/logic/EEPROM/I2c_eeprom.bdf" { { 208 -48 120 224 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.105 ns) + CELL(0.970 ns) 4.215 ns i2c_top:inst\|clk_div 2 REG LCFF_X33_Y7_N1 2 " "Info: 2: + IC(2.105 ns) + CELL(0.970 ns) = 4.215 ns; Loc. = LCFF_X33_Y7_N1; Fanout = 2; REG Node = 'i2c_top:inst\|clk_div'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.075 ns" { clk1 i2c_top:inst|clk_div } "NODE_NAME" } } { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.000 ns) 5.402 ns i2c_top:inst\|clk_div~clkctrl 3 COMB CLKCTRL_G4 115 " "Info: 3: + IC(1.187 ns) + CELL(0.000 ns) = 5.402 ns; Loc. = CLKCTRL_G4; Fanout = 115; COMB Node = 'i2c_top:inst\|clk_div~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl } "NODE_NAME" } } { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.666 ns) 6.947 ns i2c_top:inst\|data_rep\[10\] 4 REG LCFF_X32_Y10_N3 1 " "Info: 4: + IC(0.879 ns) + CELL(0.666 ns) = 6.947 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 1; REG Node = 'i2c_top:inst\|data_rep\[10\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.545 ns" { i2c_top:inst|clk_div~clkctrl i2c_top:inst|data_rep[10] } "NODE_NAME" } } { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 187 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 39.96 % ) " "Info: Total cell delay = 2.776 ns ( 39.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.171 ns ( 60.04 % ) " "Info: Total interconnect delay = 4.171 ns ( 60.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.947 ns" { clk1 i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl i2c_top:inst|data_rep[10] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.947 ns" { clk1 {} clk1~combout {} i2c_top:inst|clk_div {} i2c_top:inst|clk_div~clkctrl {} i2c_top:inst|data_rep[10] {} } { 0.000ns 0.000ns 2.105ns 1.187ns 0.879ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 187 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.492 ns + Longest register pin " "Info: + Longest register to pin delay is 13.492 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_top:inst\|data_rep\[10\] 1 REG LCFF_X32_Y10_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y10_N3; Fanout = 1; REG Node = 'i2c_top:inst\|data_rep\[10\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|data_rep[10] } "NODE_NAME" } } { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 187 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.483 ns) + CELL(0.651 ns) 2.134 ns hc164_driver:inst1\|Mux1~13 2 COMB LCCOMB_X33_Y9_N10 1 " "Info: 2: + IC(1.483 ns) + CELL(0.651 ns) = 2.134 ns; Loc. = LCCOMB_X33_Y9_N10; Fanout = 1; COMB Node = 'hc164_driver:inst1\|Mux1~13'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.134 ns" { i2c_top:inst|data_rep[10] hc164_driver:inst1|Mux1~13 } "NODE_NAME" } } { "hc164_driver.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/hc164_driver.v" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.402 ns) + CELL(0.651 ns) 3.187 ns hc164_driver:inst1\|Mux1~14 3 COMB LCCOMB_X33_Y9_N28 7 " "Info: 3: + IC(0.402 ns) + CELL(0.651 ns) = 3.187 ns; Loc. = LCCOMB_X33_Y9_N28; Fanout = 7; COMB Node = 'hc164_driver:inst1\|Mux1~14'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.053 ns" { hc164_driver:inst1|Mux1~13 hc164_driver:inst1|Mux1~14 } "NODE_NAME" } } { "hc164_driver.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/hc164_driver.v" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.401 ns) + CELL(0.650 ns) 5.238 ns hc164_driver:inst1\|WideOr4~23 4 COMB LCCOMB_X31_Y8_N24 1 " "Info: 4: + IC(1.401 ns) + CELL(0.650 ns) = 5.238 ns; Loc. = LCCOMB_X31_Y8_N24; Fanout = 1; COMB Node = 'hc164_driver:inst1\|WideOr4~23'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.051 ns" { hc164_driver:inst1|Mux1~14 hc164_driver:inst1|WideOr4~23 } "NODE_NAME" } } { "hc164_driver.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/hc164_driver.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.529 ns) 6.844 ns hc164_driver:inst1\|Mux5~287 5 COMB LCCOMB_X31_Y9_N26 1 " "Info: 5: + IC(1.077 ns) + CELL(0.529 ns) = 6.844 ns; Loc. = LCCOMB_X31_Y9_N26; Fanout = 1; COMB Node = 'hc164_driver:inst1\|Mux5~287'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.606 ns" { hc164_driver:inst1|WideOr4~23 hc164_driver:inst1|Mux5~287 } "NODE_NAME" } } { "hc164_driver.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/hc164_driver.v" 175 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.624 ns) 7.841 ns hc164_driver:inst1\|Mux5~289 6 COMB LCCOMB_X31_Y9_N2 1 " "Info: 6: + IC(0.373 ns) + CELL(0.624 ns) = 7.841 ns; Loc. = LCCOMB_X31_Y9_N2; Fanout = 1; COMB Node = 'hc164_driver:inst1\|Mux5~289'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.997 ns" { hc164_driver:inst1|Mux5~287 hc164_driver:inst1|Mux5~289 } "NODE_NAME" } } { "hc164_driver.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/hc164_driver.v" 175 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.358 ns) + CELL(0.206 ns) 8.405 ns hc164_driver:inst1\|Mux5~292 7 COMB LCCOMB_X31_Y9_N0 1 " "Info: 7: + IC(0.358 ns) + CELL(0.206 ns) = 8.405 ns; Loc. = LCCOMB_X31_Y9_N0; Fanout = 1; COMB Node = 'hc164_driver:inst1\|Mux5~292'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.564 ns" { hc164_driver:inst1|Mux5~289 hc164_driver:inst1|Mux5~292 } "NODE_NAME" } } { "hc164_driver.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/hc164_driver.v" 175 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.817 ns) + CELL(3.270 ns) 13.492 ns HC_SI 8 PIN PIN_152 0 " "Info: 8: + IC(1.817 ns) + CELL(3.270 ns) = 13.492 ns; Loc. = PIN_152; Fanout = 0; PIN Node = 'HC_SI'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.087 ns" { hc164_driver:inst1|Mux5~292 HC_SI } "NODE_NAME" } } { "I2c_eeprom.bdf" "" { Schematic "D:/Altera/release/Demo/logic/EEPROM/I2c_eeprom.bdf" { { 312 1056 1232 328 "HC_SI" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.581 ns ( 48.78 % ) " "Info: Total cell delay = 6.581 ns ( 48.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.911 ns ( 51.22 % ) " "Info: Total interconnect delay = 6.911 ns ( 51.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "13.492 ns" { i2c_top:inst|data_rep[10] hc164_driver:inst1|Mux1~13 hc164_driver:inst1|Mux1~14 hc164_driver:inst1|WideOr4~23 hc164_driver:inst1|Mux5~287 hc164_driver:inst1|Mux5~289 hc164_driver:inst1|Mux5~292 HC_SI } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "13.492 ns" { i2c_top:inst|data_rep[10] {} hc164_driver:inst1|Mux1~13 {} hc164_driver:inst1|Mux1~14 {} hc164_driver:inst1|WideOr4~23 {} hc164_driver:inst1|Mux5~287 {} hc164_driver:inst1|Mux5~289 {} hc164_driver:inst1|Mux5~292 {} HC_SI {} } { 0.000ns 1.483ns 0.402ns 1.401ns 1.077ns 0.373ns 0.358ns 1.817ns } { 0.000ns 0.651ns 0.651ns 0.650ns 0.529ns 0.624ns 0.206ns 3.270ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.947 ns" { clk1 i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl i2c_top:inst|data_rep[10] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.947 ns" { clk1 {} clk1~combout {} i2c_top:inst|clk_div {} i2c_top:inst|clk_div~clkctrl {} i2c_top:inst|data_rep[10] {} } { 0.000ns 0.000ns 2.105ns 1.187ns 0.879ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "13.492 ns" { i2c_top:inst|data_rep[10] hc164_driver:inst1|Mux1~13 hc164_driver:inst1|Mux1~14 hc164_driver:inst1|WideOr4~23 hc164_driver:inst1|Mux5~287 hc164_driver:inst1|Mux5~289 hc164_driver:inst1|Mux5~292 HC_SI } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "13.492 ns" { i2c_top:inst|data_rep[10] {} hc164_driver:inst1|Mux1~13 {} hc164_driver:inst1|Mux1~14 {} hc164_driver:inst1|WideOr4~23 {} hc164_driver:inst1|Mux5~287 {} hc164_driver:inst1|Mux5~289 {} hc164_driver:inst1|Mux5~292 {} HC_SI {} } { 0.000ns 1.483ns 0.402ns 1.401ns 1.077ns 0.373ns 0.358ns 1.817ns } { 0.000ns 0.651ns 0.651ns 0.650ns 0.529ns 0.624ns 0.206ns 3.270ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_state.sh8out_bit0 pld_CLEAR_n clk1 3.229 ns register " "Info: th for register \"i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_state.sh8out_bit0\" (data pin = \"pld_CLEAR_n\", clock pin = \"clk1\") is 3.229 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 6.949 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 6.949 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk1 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "I2c_eeprom.bdf" "" { Schematic "D:/Altera/release/Demo/logic/EEPROM/I2c_eeprom.bdf" { { 208 -48 120 224 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.105 ns) + CELL(0.970 ns) 4.215 ns i2c_top:inst\|clk_div 2 REG LCFF_X33_Y7_N1 2 " "Info: 2: + IC(2.105 ns) + CELL(0.970 ns) = 4.215 ns; Loc. = LCFF_X33_Y7_N1; Fanout = 2; REG Node = 'i2c_top:inst\|clk_div'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.075 ns" { clk1 i2c_top:inst|clk_div } "NODE_NAME" } } { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.000 ns) 5.402 ns i2c_top:inst\|clk_div~clkctrl 3 COMB CLKCTRL_G4 115 " "Info: 3: + IC(1.187 ns) + CELL(0.000 ns) = 5.402 ns; Loc. = CLKCTRL_G4; Fanout = 115; COMB Node = 'i2c_top:inst\|clk_div~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl } "NODE_NAME" } } { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.881 ns) + CELL(0.666 ns) 6.949 ns i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_state.sh8out_bit0 4 REG LCFF_X30_Y9_N21 4 " "Info: 4: + IC(0.881 ns) + CELL(0.666 ns) = 6.949 ns; Loc. = LCFF_X30_Y9_N21; Fanout = 4; REG Node = 'i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_state.sh8out_bit0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.547 ns" { i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0 } "NODE_NAME" } } { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 39.95 % ) " "Info: Total cell delay = 2.776 ns ( 39.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.173 ns ( 60.05 % ) " "Info: Total interconnect delay = 4.173 ns ( 60.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.949 ns" { clk1 i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.949 ns" { clk1 {} clk1~combout {} i2c_top:inst|clk_div {} i2c_top:inst|clk_div~clkctrl {} i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0 {} } { 0.000ns 0.000ns 2.105ns 1.187ns 0.881ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 30 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.026 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.026 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns pld_CLEAR_n 1 PIN PIN_24 21 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 21; PIN Node = 'pld_CLEAR_n'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { pld_CLEAR_n } "NODE_NAME" } } { "I2c_eeprom.bdf" "" { Schematic "D:/Altera/release/Demo/logic/EEPROM/I2c_eeprom.bdf" { { 224 -48 120 240 "pld_CLEAR_n" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.041 ns) + CELL(0.855 ns) 4.026 ns i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_state.sh8out_bit0 2 REG LCFF_X30_Y9_N21 4 " "Info: 2: + IC(2.041 ns) + CELL(0.855 ns) = 4.026 ns; Loc. = LCFF_X30_Y9_N21; Fanout = 4; REG Node = 'i2c_top:inst\|i2c_wr:i2c_wr_inst\|sh8out_state.sh8out_bit0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.896 ns" { pld_CLEAR_n i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0 } "NODE_NAME" } } { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.985 ns ( 49.30 % ) " "Info: Total cell delay = 1.985 ns ( 49.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.041 ns ( 50.70 % ) " "Info: Total interconnect delay = 2.041 ns ( 50.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.026 ns" { pld_CLEAR_n i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.026 ns" { pld_CLEAR_n {} pld_CLEAR_n~combout {} i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0 {} } { 0.000ns 0.000ns 2.041ns } { 0.000ns 1.130ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.949 ns" { clk1 i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.949 ns" { clk1 {} clk1~combout {} i2c_top:inst|clk_div {} i2c_top:inst|clk_div~clkctrl {} i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0 {} } { 0.000ns 0.000ns 2.105ns 1.187ns 0.881ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.026 ns" { pld_CLEAR_n i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.026 ns" { pld_CLEAR_n {} pld_CLEAR_n~combout {} i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0 {} } { 0.000ns 0.000ns 2.041ns } { 0.000ns 1.130ns 0.855ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}