i2c_eeprom.tan.qmsg

使用VHDL编写的操作EEPROM来控制iic的读写操作

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "I2c_eeprom.bdf" "" { Schematic "D:/Altera/release/Demo/logic/EEPROM/I2c_eeprom.bdf" { { 208 -48 120 224 "clk1" "" } } } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "i2c_top:inst\|clk_div " "Info: Detected ripple clock \"i2c_top:inst\|clk_div\" as buffer" {  } { { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "i2c_top:inst\|clk_div" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register i2c_top:inst\|i2c_wr:i2c_wr_inst\|scl register i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_bit 114.05 MHz 8.768 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 114.05 MHz between source register \"i2c_top:inst\|i2c_wr:i2c_wr_inst\|scl\" and destination register \"i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_bit\" (period= 8.768 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.120 ns + Longest register register " "Info: + Longest register to register delay is 4.120 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_top:inst\|i2c_wr:i2c_wr_inst\|scl 1 REG LCFF_X29_Y11_N25 35 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y11_N25; Fanout = 35; REG Node = 'i2c_top:inst\|i2c_wr:i2c_wr_inst\|scl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_top:inst|i2c_wr:i2c_wr_inst|scl } "NODE_NAME" } } { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.927 ns) + CELL(0.370 ns) 2.297 ns i2c_top:inst\|i2c_wr:i2c_wr_inst\|Selector82~173 2 COMB LCCOMB_X28_Y11_N12 1 " "Info: 2: + IC(1.927 ns) + CELL(0.370 ns) = 2.297 ns; Loc. = LCCOMB_X28_Y11_N12; Fanout = 1; COMB Node = 'i2c_top:inst\|i2c_wr:i2c_wr_inst\|Selector82~173'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.297 ns" { i2c_top:inst|i2c_wr:i2c_wr_inst|scl i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~173 } "NODE_NAME" } } { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(0.651 ns) 4.012 ns i2c_top:inst\|i2c_wr:i2c_wr_inst\|Selector82~175 3 COMB LCCOMB_X30_Y11_N2 1 " "Info: 3: + IC(1.064 ns) + CELL(0.651 ns) = 4.012 ns; Loc. = LCCOMB_X30_Y11_N2; Fanout = 1; COMB Node = 'i2c_top:inst\|i2c_wr:i2c_wr_inst\|Selector82~175'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.715 ns" { i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~173 i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~175 } "NODE_NAME" } } { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.120 ns i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_bit 4 REG LCFF_X30_Y11_N3 3 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 4.120 ns; Loc. = LCFF_X30_Y11_N3; Fanout = 3; REG Node = 'i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_bit'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~175 i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit } "NODE_NAME" } } { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.129 ns ( 27.40 % ) " "Info: Total cell delay = 1.129 ns ( 27.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.991 ns ( 72.60 % ) " "Info: Total interconnect delay = 2.991 ns ( 72.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.120 ns" { i2c_top:inst|i2c_wr:i2c_wr_inst|scl i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~173 i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~175 i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.120 ns" { i2c_top:inst|i2c_wr:i2c_wr_inst|scl {} i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~173 {} i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~175 {} i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit {} } { 0.000ns 1.927ns 1.064ns 0.000ns } { 0.000ns 0.370ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 6.965 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 6.965 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk1 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "I2c_eeprom.bdf" "" { Schematic "D:/Altera/release/Demo/logic/EEPROM/I2c_eeprom.bdf" { { 208 -48 120 224 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.105 ns) + CELL(0.970 ns) 4.215 ns i2c_top:inst\|clk_div 2 REG LCFF_X33_Y7_N1 2 " "Info: 2: + IC(2.105 ns) + CELL(0.970 ns) = 4.215 ns; Loc. = LCFF_X33_Y7_N1; Fanout = 2; REG Node = 'i2c_top:inst\|clk_div'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.075 ns" { clk1 i2c_top:inst|clk_div } "NODE_NAME" } } { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.000 ns) 5.402 ns i2c_top:inst\|clk_div~clkctrl 3 COMB CLKCTRL_G4 115 " "Info: 3: + IC(1.187 ns) + CELL(0.000 ns) = 5.402 ns; Loc. = CLKCTRL_G4; Fanout = 115; COMB Node = 'i2c_top:inst\|clk_div~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl } "NODE_NAME" } } { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.897 ns) + CELL(0.666 ns) 6.965 ns i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_bit 4 REG LCFF_X30_Y11_N3 3 " "Info: 4: + IC(0.897 ns) + CELL(0.666 ns) = 6.965 ns; Loc. = LCFF_X30_Y11_N3; Fanout = 3; REG Node = 'i2c_top:inst\|i2c_wr:i2c_wr_inst\|stop_state.stop_bit'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.563 ns" { i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit } "NODE_NAME" } } { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 39.86 % ) " "Info: Total cell delay = 2.776 ns ( 39.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.189 ns ( 60.14 % ) " "Info: Total interconnect delay = 4.189 ns ( 60.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.965 ns" { clk1 i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.965 ns" { clk1 {} clk1~combout {} i2c_top:inst|clk_div {} i2c_top:inst|clk_div~clkctrl {} i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit {} } { 0.000ns 0.000ns 2.105ns 1.187ns 0.897ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 6.965 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 6.965 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk1 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "I2c_eeprom.bdf" "" { Schematic "D:/Altera/release/Demo/logic/EEPROM/I2c_eeprom.bdf" { { 208 -48 120 224 "clk1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.105 ns) + CELL(0.970 ns) 4.215 ns i2c_top:inst\|clk_div 2 REG LCFF_X33_Y7_N1 2 " "Info: 2: + IC(2.105 ns) + CELL(0.970 ns) = 4.215 ns; Loc. = LCFF_X33_Y7_N1; Fanout = 2; REG Node = 'i2c_top:inst\|clk_div'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.075 ns" { clk1 i2c_top:inst|clk_div } "NODE_NAME" } } { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.000 ns) 5.402 ns i2c_top:inst\|clk_div~clkctrl 3 COMB CLKCTRL_G4 115 " "Info: 3: + IC(1.187 ns) + CELL(0.000 ns) = 5.402 ns; Loc. = CLKCTRL_G4; Fanout = 115; COMB Node = 'i2c_top:inst\|clk_div~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl } "NODE_NAME" } } { "i2c_top.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_top.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.897 ns) + CELL(0.666 ns) 6.965 ns i2c_top:inst\|i2c_wr:i2c_wr_inst\|scl 4 REG LCFF_X29_Y11_N25 35 " "Info: 4: + IC(0.897 ns) + CELL(0.666 ns) = 6.965 ns; Loc. = LCFF_X29_Y11_N25; Fanout = 35; REG Node = 'i2c_top:inst\|i2c_wr:i2c_wr_inst\|scl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.563 ns" { i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|scl } "NODE_NAME" } } { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 39.86 % ) " "Info: Total cell delay = 2.776 ns ( 39.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.189 ns ( 60.14 % ) " "Info: Total interconnect delay = 4.189 ns ( 60.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.965 ns" { clk1 i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|scl } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.965 ns" { clk1 {} clk1~combout {} i2c_top:inst|clk_div {} i2c_top:inst|clk_div~clkctrl {} i2c_top:inst|i2c_wr:i2c_wr_inst|scl {} } { 0.000ns 0.000ns 2.105ns 1.187ns 0.897ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.965 ns" { clk1 i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.965 ns" { clk1 {} clk1~combout {} i2c_top:inst|clk_div {} i2c_top:inst|clk_div~clkctrl {} i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit {} } { 0.000ns 0.000ns 2.105ns 1.187ns 0.897ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.965 ns" { clk1 i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|scl } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.965 ns" { clk1 {} clk1~combout {} i2c_top:inst|clk_div {} i2c_top:inst|clk_div~clkctrl {} i2c_top:inst|i2c_wr:i2c_wr_inst|scl {} } { 0.000ns 0.000ns 2.105ns 1.187ns 0.897ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 33 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 19 -1 0 } } { "i2c_wr.v" "" { Text "D:/Altera/release/Demo/logic/EEPROM/i2c_wr.v" 33 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.120 ns" { i2c_top:inst|i2c_wr:i2c_wr_inst|scl i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~173 i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~175 i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.120 ns" { i2c_top:inst|i2c_wr:i2c_wr_inst|scl {} i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~173 {} i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~175 {} i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit {} } { 0.000ns 1.927ns 1.064ns 0.000ns } { 0.000ns 0.370ns 0.651ns 0.108ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.965 ns" { clk1 i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.965 ns" { clk1 {} clk1~combout {} i2c_top:inst|clk_div {} i2c_top:inst|clk_div~clkctrl {} i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit {} } { 0.000ns 0.000ns 2.105ns 1.187ns 0.897ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.965 ns" { clk1 i2c_top:inst|clk_div i2c_top:inst|clk_div~clkctrl i2c_top:inst|i2c_wr:i2c_wr_inst|scl } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.965 ns" { clk1 {} clk1~combout {} i2c_top:inst|clk_div {} i2c_top:inst|clk_div~clkctrl {} i2c_top:inst|i2c_wr:i2c_wr_inst|scl {} } { 0.000ns 0.000ns 2.105ns 1.187ns 0.897ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}