i2c_eeprom.fit.rpt

使用VHDL编写的操作EEPROM来控制iic的读写操作

; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                  ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Maximum number of global clocks allowed                            ; -1                             ; -1                             ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Fitter Partition Preservation Settings                                                                 ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Name ; # Preserved Nodes ; # Nodes ; Preservation Level Requested ; Netlist Type Used      ; Hierarchy ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Top  ; 0                 ; 437     ; Placement and Routing        ; Post-Synthesis Netlist ;           ;
+------+-------------------+---------+------------------------------+------------------------+-----------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/Altera/release/Demo/logic/EEPROM/I2c_eeprom.pin.


+----------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                    ;
+---------------------------------------------+------------------------------------+
; Resource                                    ; Usage                              ;
+---------------------------------------------+------------------------------------+
; Total logic elements                        ; 287 / 8,256 ( 3 % )                ;
;     -- Combinational with no register       ; 134                                ;
;     -- Register only                        ; 9                                  ;
;     -- Combinational with a register        ; 144                                ;
;                                             ;                                    ;
; Logic element usage by number of LUT inputs ;                                    ;
;     -- 4 input functions                    ; 162                                ;
;     -- 3 input functions                    ; 34                                 ;
;     -- <=2 input functions                  ; 82                                 ;
;     -- Register only                        ; 9                                  ;
;                                             ;                                    ;
; Logic elements by mode                      ;                                    ;
;     -- normal mode                          ; 227                                ;
;     -- arithmetic mode                      ; 51                                 ;
;                                             ;                                    ;
; Total registers*                            ; 153 / 8,646 ( 2 % )                ;
;     -- Dedicated logic registers            ; 153 / 8,256 ( 2 % )                ;
;     -- I/O registers                        ; 0 / 390 ( 0 % )                    ;
;                                             ;                                    ;
; Total LABs:  partially or completely used   ; 22 / 516 ( 4 % )                   ;
; User inserted logic elements                ; 0                                  ;
; Virtual pins                                ; 0                                  ;
; I/O pins                                    ; 6 / 138 ( 4 % )                    ;
;     -- Clock pins                           ; 1 / 4 ( 25 % )                     ;
; Global signals                              ; 3                                  ;
; M4Ks                                        ; 0 / 36 ( 0 % )                     ;
; Total memory bits                           ; 0 / 165,888 ( 0 % )                ;
; Total RAM block bits                        ; 0 / 165,888 ( 0 % )                ;
; Embedded Multiplier 9-bit elements          ; 0 / 36 ( 0 % )                     ;
; PLLs                                        ; 0 / 2 ( 0 % )                      ;
; Global clocks                               ; 3 / 8 ( 38 % )                     ;
; JTAGs                                       ; 0 / 1 ( 0 % )                      ;
; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%                       ;
; Peak interconnect usage (total/H/V)         ; 2% / 2% / 2%                       ;
; Maximum fan-out node                        ; i2c_top:inst|clk_div~clkctrl       ;
; Maximum fan-out                             ; 115                                ;
; Highest non-global fan-out signal           ; i2c_top:inst|i2c_wr:i2c_wr_inst|ff ;
; Highest non-global fan-out                  ; 51                                 ;
; Total fan-out                               ; 1421                               ;
; Average fan-out                             ; 3.14                               ;
+---------------------------------------------+------------------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                        ;
+-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name        ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk1        ; 23    ; 1        ; 0            ; 9            ; 0           ; 2                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;