i2c_eeprom.tan.rpt

使用VHDL编写的操作EEPROM来控制iic的读写操作

+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk1            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk1'                                                                                                                                                                                                                                                                                                           ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                   ; To                                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 114.05 MHz ( period = 8.768 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit      ; clk1       ; clk1     ; None                        ; None                      ; 4.120 ns                ;
; N/A                                     ; 120.16 MHz ( period = 8.322 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_end    ; clk1       ; clk1     ; None                        ; None                      ; 3.875 ns                ;
; N/A                                     ; 120.16 MHz ( period = 8.322 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit0   ; clk1       ; clk1     ; None                        ; None                      ; 3.875 ns                ;
; N/A                                     ; 120.16 MHz ( period = 8.322 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit1   ; clk1       ; clk1     ; None                        ; None                      ; 3.875 ns                ;
; N/A                                     ; 120.16 MHz ( period = 8.322 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit2   ; clk1       ; clk1     ; None                        ; None                      ; 3.875 ns                ;
; N/A                                     ; 120.16 MHz ( period = 8.322 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit3   ; clk1       ; clk1     ; None                        ; None                      ; 3.875 ns                ;
; N/A                                     ; 120.16 MHz ( period = 8.322 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit4   ; clk1       ; clk1     ; None                        ; None                      ; 3.875 ns                ;
; N/A                                     ; 120.16 MHz ( period = 8.322 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit5   ; clk1       ; clk1     ; None                        ; None                      ; 3.875 ns                ;
; N/A                                     ; 120.16 MHz ( period = 8.322 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit6   ; clk1       ; clk1     ; None                        ; None                      ; 3.875 ns                ;
; N/A                                     ; 125.66 MHz ( period = 7.958 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[3]            ; clk1       ; clk1     ; None                        ; None                      ; 3.696 ns                ;
; N/A                                     ; 125.66 MHz ( period = 7.958 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[2]            ; clk1       ; clk1     ; None                        ; None                      ; 3.696 ns                ;
; N/A                                     ; 125.66 MHz ( period = 7.958 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[1]            ; clk1       ; clk1     ; None                        ; None                      ; 3.696 ns                ;
; N/A                                     ; 125.66 MHz ( period = 7.958 ns )                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl                    ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[0]            ; clk1       ; clk1     ; None                        ; None                      ; 3.696 ns                ;