led.v

在EPM570开发板上实现LED控制的程序

module led(sel,seg,rst,clk,wr,cs,rd,cpu_data,addr);
input clk,rst,wr,cs,rd,a;
output [7:0]sel,seg;
inout [15:0]cpu_data;
input [3:0]addr;
reg [7:0]sel,seg;
reg [15:0]set,set1;

reg wr1;
always@(posedge clk)
wr1<=wr;
always@(posedge clk or negedge rst)
if(!rst)
set<=16'h0025;
else if((wr1==0||addr==)&&cs==0)
set<=cpu_data;
else
set<=set1;
always@(posedge clk)
set1<=set;

assign cpu_data=(rd==0&cs==0)?(set+1'b1):16'hz;

reg [7:0]TAB[15:0];
reg [16:0]count1;
always@(posedge clk or negedge rst)
begin
	if(!rst)
	   begin
	   TAB[0] <=8'b11000000;
	   TAB[1] <= 8'b11111001;
	   TAB[2] <= 8'b10100100;
       TAB[3] <= 8'b10110000;
	   TAB[4] <= 8'b10011001;
	   TAB[5] <= 8'b10010010;
	   TAB[6] <= 8'b10000010;
	   TAB[7] <= 8'b11011000;
	   TAB[8] <= 8'b10000000;
	   TAB[9] <= 8'b10010000;
	   TAB[10] <= 8'b10001000;
	   TAB[11] <= 8'b10000011;
	   TAB[12] <= 8'b11000110;
	   TAB[13] <= 8'b10100001;
	   TAB[14] <= 8'b10000110;
	   TAB[15] <= 8'b10001110;
	   end
end

always@(posedge clk or negedge rst)
if(!rst)
count1<=0;
else
count1<=count1+1'b1;
	   
always@(posedge clk or negedge rst)
begin
   if(!rst)
   begin
      sel<=8'h00;
	   seg<=8'h00;
	end
	else
	      case(count1[16:15])
	      0:
	      begin
	      sel<=8'b00001110;
	      seg<=TAB[set[15:12]];
	      end
	      1:
	      begin
	      sel<=8'b00001101;
	      seg<=TAB[set[11:8]];
	      end
	      2:
	      begin
	      sel<=8'b00001011;
	      seg<=TAB[set[7:4]];
	      end
	      3:
	      begin
	      sel<=8'b00000111;
	      seg<=TAB[set[3:0]];
	      end
	      endcase
end

endmodule