clk_div.vhd

游戏代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY clk_div IS
	PORT(clk,sel:			 IN STD_LOGIC;--clk为1MHz高频时钟输入，sel为分频输出选择
		 clk_out:OUT STD_LOGIC);
END ENTITY;

ARCHITECTURE main OF clk_div IS
SIGNAL clk_out_2hz,clk_out_5hz:STD_LOGIC;
BEGIN
	PROCESS(clk)
	VARIABLE count:integer range 0 to 99999;--记数器，分为5Hz
	BEGIN
		if(rising_edge(clk)) then
			if(count = 99999) then 
				count := 0;
				clk_out_5hz <= NOT clk_out_5hz;
			else
				count := count + 1;
			end if;
		end if;
	END PROCESS;
	
	PROCESS(clk_out_5hz) --再把5Hz信号分成2.5Hz
	BEGIN
		if(rising_edge(clk_out_5hz)) then
			clk_out_2hz <= NOT clk_out_2hz;
		end if;
	END PROCESS;
	WITH sel SELECT-- 选择输出时钟
	clk_out <= clk_out_2hz when '0',
			   clk_out_5hz when '1';
END ARCHITECTURE;