total_stat.vhd

来自「游戏代码」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY total_stat IS
	port(p1total,p2total,reset,reset_all,ends: 	 IN STD_LOGIC;--总比分，清零，复位，结束标志
		 	 total1,total2:	    OUT integer range 0 to 4);
END ENTITY;
ARCHITECTURE main OF total_stat IS
SIGNAL total_1,total_2:integer range 0 to 4;
BEGIN
	PROCESS(p1total,reset,ends,reset_all)
	BEGIN
		if(reset_all = '1') then -- 全局复位
			   total_1 <= 0;--比分清零
		elsif(reset='1') then -- 裁判按下开始键
			if(ends='1') then -- 判断比赛是否全部结束
				total_1 <= 0; -- 比赛重新开始，总比分清零
			end if;
		elsif(rising_edge(p1total)) then
			total_1 <= total_1 + 1;
		end if;
	END PROCESS;
	
	PROCESS(p2total,reset,ends,reset_all)
	BEGIN
		if(reset_all = '1') then
			total_2 <=0;
		elsif(reset='1') then
			if(ends='1') then 
				total_2 <= 0;
			end if;
		elsif(rising_edge(p2total)) then
			total_2 <= total_2 + 1;
		end if;
	END PROCESS;
	
	
	total1 <= total_1;
	total2 <= total_2;
END ARCHITECTURE;