score_stat.vhd

游戏代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY score_stat IS
	port(p1win,p2win,reset,reset_all: 	 IN STD_LOGIC;--得分信号，比分清零，全局复位
		 	 score1,score2:	    OUT integer range 0 to 11);
END ENTITY;
ARCHITECTURE main OF score_stat IS
SIGNAL score_1,score_2:integer range 0 to 11;
BEGIN
	PROCESS(p1win,reset,reset_all)
	BEGIN
		if(reset='1' OR reset_all = '1') then score_1 <= 0;-- 复位，比分清零
		elsif(rising_edge(p1win)) then -- 检测到P1得分信号（高电平）
			score_1 <= score_1 + 1;
		end if;
	END PROCESS;
	
	PROCESS(p2win,reset,reset_all)
	BEGIN
		if(reset='1' OR reset_all = '1') then score_2 <= 0;
		elsif(rising_edge(p2win)) then
			score_2 <= score_2 + 1;
		end if;
	END PROCESS;
	score1 <= score_1;
	score2 <= score_2;
END ARCHITECTURE;