📄 change.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY change IS
PORT(first:IN STD_LOGIC;-- 首发是谁
score1,score2: IN integer range 0 to 11;-- 当前比分
total1,total2: IN integer range 0 to 4;-- 当前总比分
total: OUT integer range 0 to 7; -- 总比分和
ends,who:OUT STD_LOGIC); -- 比赛是否结束标志,当前发球权
END ENTITY;
ARCHITECTURE main OF change IS
SIGNAL who_temp,first_temp:STD_LOGIC;
SIGNAL temp:integer range 0 to 21;
BEGIN
first_temp <= first;
temp <= score1 + score2;--当前比分和
ends <= '1' when total1 = 4 OR total2 = 4 -- 当一方获胜4局时比赛结束
else '0';
who_temp <= first_temp when (temp=0 OR temp=1 OR temp=4 OR temp=5 OR temp=8 OR temp=9 OR temp=12 OR temp=13 OR temp=16 OR temp=17 OR temp=20)
else NOT first_temp when (temp=2 OR temp=3 OR temp=6 OR temp=7 OR temp=10 OR temp=11 OR temp=14 OR temp=15 OR temp=18 OR temp=19)
else who_temp;--根据总比分和交换发球权
who <= who_temp;
total <= total1 + total2;
END ARCHITECTURE;
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